Physical Design & Signoff glossary

Physical design and signoff terms describe how a netlist becomes a layout ready for manufacture: floorplanning, placement, clock tree synthesis, routing, and the timing, power, reliability and physical checks a design must pass before tape-out.

Physical design engineers and project leads use them to track closure, explain why a block misses timing or power, and agree when a design is clean enough to send to the foundry.

90 terms in 13 groups, 30 with a full explanation and examples. Each term has its own page.

Clock tree synthesis

Clock skew: The difference in clock arrival time between two sinks, most importantly between the launching and capturing flops of a path.
CTS: Clock Tree SynthesisIn depth: The automated construction of the clock distribution network, inserting and placing clock buffers and inverters to deliver the clock to every sink within skew, latency, slew and power targets.
ICG: Integrated Clock Gating cell: A library cell combining a latch and an AND or OR gate that gates the clock to a bank of flops without producing glitches, enabling dynamic power savings when the flops need not update.
Insertion delay: The propagation time from the clock source or block boundary to a clock sink, also called clock latency.
Useful skew: Deliberately unbalancing the clock tree so a flop with a tight setup path receives its clock later, borrowing time from the adjacent stage.

ECO

Base layer ECO: Base layer Engineering Change Order: A change requiring new transistor-level masks because the fix cannot be built from existing spare devices.
ECO route: Engineering Change Order routing: Incremental routing that connects newly added or modified instances while leaving existing routes untouched wherever possible, so that previously signed-off timing and parasitics remain largely valid.
Functional ECO: Functional Engineering Change Order: A logic change applied to an already implemented design, derived by comparing the new RTL against the existing netlist and patching only the differing logic so that the rest of the physical impleme...
Metal ECO: Metal Engineering Change Order: A design change implemented by modifying only metal and via masks, reusing existing transistors from spare or gate array fill cells.
Spare cell: An unused logic gate or flop deliberately scattered through the placement so that a later functional change can be implemented by rewiring metal to existing transistors instead of re-spinning base...

Floorplanning

Abutment: Placing two physical blocks or cells edge to edge so that their power rails, wells and signal pins connect directly without intervening routing.
Aspect ratioIn depth: The ratio of a block's height to its width.
Core area: The region inside the IO ring where standard cell rows and macros are legally placed.
Die sizeIn depth: The physical area of a single chip on the wafer, set by whichever dominates: total logic and memory area, IO and bump count, or analogue and power structures.
ESD clamp: Electrostatic Discharge clamp: A large transistor or thyristor structure between supply and ground that turns on during an electrostatic event to shunt the discharge current away from sensitive circuitry, then stays off in norma...
Halo: A keep-out margin drawn around a macro in which standard cells may not be placed, reserving space for pin access routing, power straps and buffering near the macro edge.
Hierarchical implementation: An implementation style where blocks are placed, routed and signed off separately and then integrated at top level using abstracts and timing models, rather than processing the whole design flat.
ILM: Interface Logic Model: A reduced model of a block that keeps only the logic and parasitics on paths touching the boundary, discarding purely internal timing.
IO ring: Input Output ring: The band of IO cells, ESD structures and power pads around the core that interfaces the die to the package, providing level translation, drive strength and electrostatic protection.
Macro placement: The task of positioning hard macros such as SRAMs, PLLs and analogue IP within a floorplan so that their pins face the logic that uses them and the remaining core stays routable and timing-clean.
Pad frame: The complete assembled ring of IO, power, ground and corner cells plus the bond pads or bumps, delivered as a physical structure that the core floorplan is fitted inside.
Physical designIn depth: The part of chip implementation that turns a synthesised netlist into a manufacturable layout: floorplanning, placement, clock tree synthesis, routing, timing closure and physical signoff.
Pin assignmentIn depth: Deciding the location, layer and order of a block's boundary pins so that top-level routing between partitions is short, congestion-free and timing-feasible.
Seal ring: A continuous ring of stacked metal and via structures around the die perimeter that blocks moisture ingress and stops dicing-induced cracks from propagating into active circuitry.
UtilisationIn depth: The fraction of available placeable core area consumed by cell and macro instances, typically quoted as a percentage.

Mask data prep

Chip finishingIn depth: The final sequence of layout steps before tapeout, including metal fill, redundant via insertion, antenna fixing, logo and text placement, seal ring attachment and final DRC and LVS on the merged d...
FracturingIn depth: Decomposing OPC-corrected polygons into the primitive shapes a mask writer can expose, typically trapezoids for variable shaped beam tools, and ordering them into the writer's job format.
MDP: Mask Data PreparationIn depth: The chain of post-tapeout steps that converts design layout into mask writer instructions, including sizing, boolean operations, OPC, mask rule checking, fracturing and jobdeck assembly.

Parasitic extraction

Coupling capacitance: Capacitance between two neighbouring signal wires rather than to ground.
Extraction corner: A named set of interconnect process assumptions, such as cmin, cmax, rcmin and rcmax, capturing metal thickness and dielectric variation.
Parasitic extractionIn depth: Deriving the resistance and capacitance of every wire and via from routed layout geometry and the process stack, producing an annotated network for timing, noise and power analysis.

Physical design views

Abstract view: A simplified view of a hard macro that shows only its outline, pins and the areas where routing is blocked, without the layout inside.

Physical verification

Antenna effect: Charge collected by a large area of exposed metal or poly during plasma processing discharging through a connected gate oxide, damaging or degrading it before upper layers complete the current path.
CAA: Critical Area Analysis: A yield analysis that computes, for each defect size, the layout area where a random particle would cause a short or an open, then convolves it with the foundry's defect density to predict random d...
Design ruleIn depth: A geometric constraint a layout must meet to be manufacturable with good yield on a given process, such as minimum width, spacing, enclosure or density.
DFM: Design for ManufacturabilityIn depth: The practice of shaping layout beyond minimum legal rules so that it prints and yields reliably, using recommended rules, via doubling, wire spreading and litho-friendly patterning.
ERC: Electrical Rule Check: Checks for electrically illegal structures in layout such as floating gates, shorted supplies, missing well or substrate ties, and unterminated inputs, which DRC and LVS will not catch on their own.
Metal fill: Dummy metal shapes added to sparse regions so each layer meets its minimum density and density-gradient rules, keeping chemical mechanical polishing uniform and etch loading consistent.
Physical verificationIn depth: The checks that a finished layout can be manufactured and matches its design: design rule checks, layout versus schematic, electrical rule checks, antenna and density checks.

Placement

Buffer insertion: Adding buffers or inverter pairs along a net to restore signal slew, break a long RC wire into shorter segments, or shift delay deliberately.
Detailed placement: The stage that refines a legalised placement with local moves and swaps, improving wirelength, timing and pin access while keeping every cell on-site and overlap-free.
Filler cell: A functionless cell inserted into gaps in standard cell rows to continue power rails, wells and implant layers so that the row remains DRC-clean and electrically continuous.
Global placement: The first placement stage, which spreads instances across the core to minimise estimated wirelength, congestion and timing cost while allowing cells to sit off-grid and overlap.
Legalisation: Snapping overlapping, off-grid cells from global placement onto legal sites and rows with no overlaps, while displacing each cell as little as possible so timing and wirelength are preserved.
Place and routeIn depth: The physical design steps that put standard cells and macros in legal positions and then connect them with metal wiring that meets timing, power and design rules.
Standard cell row: A horizontal track of fixed height in the core into which standard cells are placed, abutting so their power and ground rails connect.
Timing-driven placement: Placement guided by path timing rather than wirelength alone, shortening nets on critical paths by weighting them more heavily or by applying explicit net delay and path constraints.

Power analysis

Dynamic powerIn depth: Power consumed by charging and discharging capacitance when nodes switch, plus short-circuit current during transitions.
Power domainIn depth: A region of the design sharing one supply net and one power state, which can be switched or scaled independently.
Power gatingIn depth: Cutting supply to an idle block using header or footer switch cells so that its leakage falls to near zero, at the cost of state loss, wake-up latency and inrush current when the block is restored.

Power integrity

Decap cell: A filler-shaped cell containing a capacitor between supply and ground, placed to supply local charge during switching and suppress dynamic voltage droop on the power grid.
Dynamic IR drop: Instantaneous supply droop caused by simultaneous switching current drawn through grid resistance and inductance, analysed with real or vectorless activity over time.
EM: ElectromigrationIn depth: The gradual displacement of metal atoms by momentum transfer from flowing electrons, thinning wires and vias until they open or extrude and short.
EM-IR analysis: Electromigration and IR drop analysis: The combined signoff step that solves the power grid for current and voltage everywhere, reporting both voltage drop at cell pins and per-segment current density against foundry electromigration li...
IR drop: Current Resistance dropIn depth: The voltage lost between the package supply and a cell's power pin due to resistance in the power delivery network.
Power gridIn depth: The network of supply and ground straps, rails, vias and rings that delivers current from package bumps to every cell.
Power integrityIn depth: How well the power delivery network supplies a steady voltage to every circuit under changing load, and the analysis that checks it from regulator through board and package to the transistors.
Power planning: Designing the power grid during floorplanning: choosing strap layers, widths, pitches and via structures, and sizing the rings and macro connections so that current density and voltage drop targets...
Static IR drop: Voltage drop computed from average current demand through the resistive power grid, ignoring time-varying effects.

Routing

CongestionIn depth: The condition where demand for routing tracks in a region exceeds supply, measured as overflow per global routing cell.
Detailed routing: The final routing stage that draws actual metal shapes and vias on-grid, honouring every spacing, width, enclosure, cut and colouring rule to produce DRC-clean connectivity.
Global routing: The routing stage that assigns each net a coarse path through a grid of routing cells and to specific layers, planning track usage and detecting congestion without drawing exact wire geometry.
NDR: Non-Default Rule: A routing rule applied to selected nets that widens the wire, increases spacing or forces multiple vias beyond the default.
Redundant via: A second via cut placed in parallel with an existing one so the connection survives a single via defect and carries current with lower resistance.
Routing track: One of the evenly spaced lines on a metal layer along which the router may draw a wire, set by that layer's pitch.
Via: A conductive vertical connection between two adjacent metal layers, formed as a patterned cut filled with tungsten or copper.

Signal integrity

Aggressor: A net whose switching injects charge into a neighbouring victim net through coupling capacitance.
CrosstalkIn depth: The disturbance induced on a victim net by capacitive coupling from a switching neighbour, appearing either as a delay change when both switch together or as a noise glitch when the victim is quiet.
Delta delay: The change in a net's propagation delay caused by crosstalk, negative when an aggressor switches in the same direction and speeds the victim, positive when it switches oppositely and slows it.
GlitchIn depth: A transient voltage excursion on a quiet net caused by a switching aggressor.
ShieldingIn depth: Routing grounded or supply-tied wires beside or above and below a sensitive net so that coupling to switching neighbours is intercepted, limiting crosstalk delay and noise on that net.
Timing window: The interval during which a net can switch, bounded by its earliest and latest possible arrival times.

Timing signoff

AOCV: Advanced On-Chip Variation: An OCV refinement where the derate factor depends on path depth and physical distance, recognising that random variation averages out over many stages while systematic variation grows with separation.
Case analysis: Fixing a control signal to a constant during timing analysis so the tool propagates that value and prunes the paths it disables.
Critical pathIn depth: The timing path with the least slack in a design or path group, which sets the maximum operating frequency.
CRPR: Clock Reconvergence Pessimism Removal: Credit applied back to a timing check for the portion of the clock path shared by launch and capture, since derating that common segment in opposite directions is physically impossible.
DeratingIn depth: Applying a multiplicative factor to cell and net delays to model variation or guard band, typically slowing the launch path and speeding the capture path for setup and the reverse for hold.
Hold time: The minimum interval a data input must remain stable after the capturing clock edge.
MMMC: Multi-Mode Multi-CornerIn depth: An analysis and optimisation setup that evaluates the design simultaneously across several functional modes and several PVT and RC corners, so that fixes for one scenario do not break another.
Path group: A named bucket of timing endpoints, typically per clock or by boundary type such as input to register or register to output, so that violations are reported and optimised separately per group.
POCV: Parametric On-Chip Variation: A statistical variation method that assigns each timing arc a delay distribution, usually a sigma value, and combines them statistically along a path rather than applying a single multiplicative de...
Setup time: The minimum interval a data input must be stable before the capturing clock edge for the flop to resolve reliably.
Slack: The margin on a timing check, computed as required time minus arrival time for setup and arrival minus required for hold.
STA: Static Timing AnalysisIn depth: Exhaustive verification of a design's timing by propagating arrival and required times through every path without simulating vectors, reporting setup, hold and design rule violations across all cor...
Timing arc: A characterised delay or constraint relationship in a library cell between two pins, such as input to output propagation, or a setup or hold requirement between data and clock.
Timing closureIn depth: The iterative process of reaching zero negative slack on every timing check across all signoff scenarios, combining placement, CTS, routing, optimisation and ECO changes until the design meets its...
Timing model: A description of a block's timing, such as delays, setup and hold requirements and their dependence on load and slew, in a form the integrator's static timing tools can use without the block's full...
TNS: Total Negative Slack: The sum of negative slack over all failing endpoints in a scenario, measuring how widespread the timing problem is rather than how deep the single worst path goes.
Transition time: The time a signal takes to swing between defined voltage thresholds, usually 10 and 90 percent or 30 and 70 percent.
WNS: Worst Negative Slack: The most negative slack value across all analysed timing paths in a given scenario, identifying the single worst violation and therefore the frequency at which the design would currently fail.

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