Process variation

Notes

Variation, not nominal performance, is usually what limits SRAM minimum operating voltage at advanced nodes.

Overview

Process variation is the natural spread in transistor and wiring dimensions, film thicknesses and doping that makes nominally identical devices behave slightly differently across a chip, a wafer and from lot to lot. Every manufacturing step contributes some, and its effect grows as features shrink, because a few atoms or nanometres become a larger share of each dimension. Foundries measure it and pass it to designers as corner and statistical models, and designs add margin so chips still work across the spread.

How it works

Variation comes from many places: gate oxide thickness, the random number and position of dopant atoms, line-edge roughness, lithography and etch, and polishing. At the leading edge, stochastic effects in EUV lithography and films only a few atoms thick add to the list. Engineers split it into systematic parts, which follow layout or position and can be modelled, and random parts, which only statistics can describe. Much apparently random variation has a traceable cause that is simply too costly to chase. Absolute variation has fallen at each node, but as a share of nominal values it has stayed flat or grown.

It also matters where variation acts. Global variation shifts a whole die or wafer together; local variation makes neighbouring devices differ, and that on-chip part has become the hardest design problem.

Foundries characterise each process and supply model files. Device corners such as typical (TT), fast-fast (FF) and slow-slow (SS) bound transistor behaviour, and wiring corners such as Cworst and RCworst bound interconnect. Combined with voltage and temperature, corners multiply quickly, and some teams report checking hundreds of combinations. Analogue designers run Monte Carlo simulations from tens to thousands of times and enlarge sensitive devices to improve matching, while timing tools model local variation statistically rather than with one flat margin, which adds pessimism and leads to overdesign.

Examples

• Foundry device corners labelled TT, FF, SS, FS and SF used to bound transistor speed in simulation.
• Interconnect corners such as Cworst and RCworst used in parasitic extraction for timing signoff.
• Monte Carlo simulation of a comparator with foundry mismatch models, leading the designer to enlarge its input pair.
• Parametric on-chip variation (POCV) in static timing analysis, replacing a single flat margin with a statistical model.
• Stochastic printing variation in EUV lithography that matters more as process windows tighten.

Related terms

• RDF
• DTCO
• Threshold voltage
• Transistor density

Where it appears on the Hub

Used on 11 pages of the Hub. In each group, the pages that mention it most come first.