Metal stack

Overview

A metal stack is the set of metal wiring and via layers that a process provides above the transistors, defined by the number of layers and each layer's thickness, pitch and material. Many processes offer several stack options, and the one chosen affects routing density, wire resistance, power delivery, cost and the number of masks. Mature processes may offer around five metal layers, while advanced logic processes can have more than ten.

How it works

The stack is built in the back end of line. Each level is a dielectric layer containing patterned metal lines, joined to the levels above and below by vias, and the dielectric, metal and via steps repeat for every layer. Copper is the usual wiring metal today; before 1998 practically all chips used aluminium.

The layers do different jobs. The lowest levels have the finest pitch and make connections inside standard cells and blocks, while upper levels carry the long global wires between blocks, along with clocks and power distribution. Designers trade routing density against resistance and capacitance, and the trade is getting harder: at advanced nodes the resistance of the lowest layers has risen sharply with each generation, and interconnect delay can make up most of a path's delay.

Foundries describe the available options in their design kits. SkyWater's open SKY130 kit, for example, lists a local interconnect layer plus five metal levels, with alternative versions of some levels, including copper variants. More layers ease routing and power distribution but add masks and process steps, while fewer layers save cost but may enlarge the die. Backside power delivery, which moves power wiring beneath the transistors, frees front-side layers for signals.

Examples

• A mature-node mixed-signal design using a five-metal stack to keep mask cost down.
• An advanced processor with more than ten metal layers, the upper ones reserved for global routing and the power grid.
• A team adding one metal layer to relieve routing congestion, accepting the cost of extra masks.
• A backside power process that moves power rails beneath the transistors, freeing front-side layers for signals.

Why it matters

The metal stack decides how dense a design can be, how well it can deliver power and how fast its long wires are, and it is fixed early because it sets mask count and the cell libraries. Physical design engineers, PDK teams, BEOL process integration engineers and product cost engineers all have a stake in the choice.

In the chip lifecycle, the stack option is chosen at architecture or project start, built into the design kit and libraries, used throughout physical design and signoff, and manufactured in the back end of the fab.

It matters most to: BEOL Process Integration Engineer, PDK Development Engineer, Physical Design Engineer, Product Cost Engineer, Standard Cell Library Engineer

Common confusions

Not the same as BEOL

BEOL is the manufacturing stage that builds the wiring. The metal stack is the particular set of layers that stage produces for a chosen process option.

Not the same as mask set

The mask set includes a mask for every metal and via layer, so the stack choice changes the mask count, but the mask set also covers all the transistor-level layers.

Sources

1. SkyWater SKY130 PDK documentation: Background (opens in a new tab), SkyWater PDK Authors, 2026-10-22
2. SkyWater SKY130 PDK documentation: Criteria and Assumptions (process stack diagram) (opens in a new tab), SkyWater PDK Authors, 2026-10-22
3. Gates Add Functionality, But Wires Create Problems (Brian Bailey, 14 May 2026) (opens in a new tab), Semiconductor Engineering, 2026-10-22
4. Back end of line (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• BEOL
• Interconnect
• Mask set

Where it appears on the Hub

Used on 8 pages of the Hub. In each group, the pages that mention it most come first.