RC delay (Resistance-capacitance delay)

Notes

Wire delay overtook gate delay as the dominant timing component around the 130 nm generation.

Overview

RC delay is the time a signal takes to travel along a wire on a chip, set by the product of the wire's resistance and its capacitance. A driver has to charge the wire's capacitance through its resistance, so more of either means a slower edge at the far end. At advanced nodes the rising resistance of very thin wires has made RC delay an increasing limit on performance, alongside the speed of the transistors themselves.

How it works

A wire's resistance equals the metal's resistivity times its length divided by its cross-sectional area, and its capacitance comes from the insulator around it: to the layers above and below and to neighbouring wires. Because both grow with length, the delay of a long unbuffered wire grows roughly with the square of its length, which is why long routes are broken up with repeaters. Timing tools estimate each net's delay from extracted resistance and capacitance, using models that build on the Elmore delay approximation from 1948.

Scaling makes matters worse. Shrinking a wire's width and height together shrinks its cross-section quadratically, so resistance per unit length rises sharply. On top of that, copper's resistivity climbs once lines become narrower than the distance electrons travel between collisions, about 40 nm in copper, because scattering increases; Samsung researchers have reported roughly a tenfold rise in line resistance relative to bulk copper below about 10 nm. The barrier that stops copper diffusing into the insulator does not shrink as fast as the line, so it takes a growing share of the wire.

The industry attacks both terms. Low-k dielectrics and, in some schemes, air gaps reduce capacitance, though low-k films are mechanically weak. Thinner barriers and alternative metals such as ruthenium are being developed to lower resistance in the narrowest wires, while wider upper metal layers carry long routes and power.

Examples

• A Qualcomm engineer, quoted in 2014, projecting that the gap between transistor delay and interconnect delay would grow about 1,000 times from the 90 nm to the 10 nm node.
• Research by Samsung and imec on ruthenium vias and wires as a lower-resistance option for the narrowest lines.
• Repeaters inserted at intervals along a long global route so that its delay grows roughly in proportion to distance.
• Parasitic extraction of a routed block producing resistance and capacitance for every net, which static timing analysis uses to compute wire delays.

Why it matters

Related terms

• Low-k dielectric
• MMP
• Copper interconnect
• Repeater

Where it appears on the Hub

Used on 12 pages of the Hub. In each group, the pages that mention it most come first.