A chip built on a pre-built base array whose transistors, lower wiring, clock and power networks and fixed blocks are designed, qualified and manufactured once, then customised for each customer in only a few metal or via layers. The vendor designs, tapes out and qualifies the base array and its design kit; each customer design, often converted from an FPGA prototype, is then implemented on that base, and only its custom layers are taped out on wafers already built up to them, which shortens turnaround and lowers the mask cost compared with a full custom chip.
Start here: what it is, how the related terms differ, what this lifecycle covers and its phases in order, then the detail.
A structured ASIC is a chip built on a pre-built base array. The vendor designs the base once: its transistors, lower wiring, clock and power networks, and fixed blocks such as memories, clock generators and input and output cells. Each customer design then needs only a few metal or via layers of its own to connect that base into its logic.
Because the base layers are shared, the vendor builds wafers up to the first customisable layer ahead of demand and holds them in a wafer bank. A customer device needs masks for its custom layers only, processed on banked wafers, so it costs less in masks and comes back sooner than a chip with every layer made for it.
Many customer designs arrive as a working FPGA prototype, converted for lower unit cost, lower power and often a longer supply life.
A structured ASIC sits between the FPGA, programmed after manufacture, and the standard cell ASIC, with every layer made for one design. From most flexible to most fixed, then the costs and changes that come with them:
| Term | What it is | How it differs |
|---|---|---|
| FPGA | A chip whose logic and routing are set by a configuration loaded after manufacture. | Nothing is made for the customer at the factory: most flexible, but usually dearer per part and higher in power. |
| FPGA-to-ASIC conversion | Moving a design proven on an FPGA onto a chip made for it, often a structured ASIC. | A route into a fixed chip, not a kind of chip. |
Structured ASIC lifecycle: 15 stages, 21 gates of its own and 9 hand-offs to the Product lifecycle, from Platform Definition to Platform Sustaining & End of Life.
15 stages, 21 gates of its own and 9 hand-offs to the Product lifecycle, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
In collaboration with The Digital Electronics Blog (opens in a new tab)
A dashed sign with a TR tag is a technical readiness review gate.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Deciding what the base array platform is for: the kinds of customer designs it serves, such as conversions from FPGA prototypes or lower volume custom chips, the process technology, the range of array sizes, the fixed blocks such as memories, clock generators and input and output cells, which layers are left for customisation and the turnaround and cost the platform must offer.
Concept approval gate, owned by the Product lifecycle (Concept approval)Platform requirements baselined gate
Defining the base array: the configurable logic cell and how the custom layers turn it into logic and registers, the routing left in the fixed layers and the routing made in the custom layers, the clock and power networks built into the base, the embedded memories and the input and output ring, and the array sizes in the family.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
Designing the base array from the frozen architecture: laying out the array tile and the configurable cells, integrating the fixed blocks such as memories, clock generators and the input and output ring with the clock and power networks, building the verification environment and the reference flow alongside, and taking the reference customer designs through a first trial of the flow.
Completing the base array design to its freeze: finishing the layout of the fixed layers, characterising the configurable cell library and its timing models, defining the platform test architecture and confirming the design against the architecture, until every planned feature is in and only reviewed fixes are accepted.
Verifying the frozen base array, its cells and fixed blocks, taking test designs through the reference flow, closing the physical checks for tape-out, and releasing the design kit that customer designs are built from: the cell library and its timing models, the rules for the custom layers and a reference flow that takes a customer netlist to custom layer masks.
Base array verification sign-off gateDesign kit released gate
Releasing the masks for the fixed base layers, building wafers up to the first customisable layer and holding them in a wafer bank, so that a customer design needs only its custom layers to be processed.
Base layer tape-out gateTR2, technical readiness reviewBase wafers built and banked gate
Finishing banked wafers with test designs that exercise the base array, measuring them against the library models, and qualifying the base for reliability so that customer designs built on it can be qualified largely by similarity.
Base array validated gateBase array qualified gateTR3, technical readiness review
Taking in a customer design, as an FPGA prototype or as RTL, and checking that it fits: which array size it needs, whether its memories, clocks and input and output can be met by the base, what timing it can reach, and what it will cost and how long it will take.
Customer design feasibility agreed gateCustomer design accepted gate, owned by the Product lifecycle (Plan approval and development commit)
Converting a design proven on an FPGA into one the base array can carry: replacing FPGA specific primitives such as block memories, arithmetic blocks, clock managers and input and output buffers with their structured ASIC equivalents, adding test logic the FPGA did not need, and proving the result equivalent to the prototype.
Synthesising the customer design to the configurable cells, inserting test, trying placement and routing on the fixed base and reviewing the netlist with the customer, until the netlist is frozen and only reviewed changes are accepted, each with its effect on timing and schedule stated.
Placing and routing the frozen netlist on the fixed base, closing timing within the routing the custom layers allow, closing test coverage, and signing off timing, physical checks and equivalence with the customer.
Releasing the masks for only the custom metal or via layers, pulling banked base wafers and processing the custom layers on them.
Testing the first parts of the customer design, shipping samples, supporting the customer while they validate them in their system, qualifying the device, largely by similarity to the qualified base array, and releasing it for production once the customer approves.
First silicon gateEngineering samples gate, owned by the Product lifecycle (Engineering samples)Samples validated gateCustomer approval gateDevice qualified gate
Building the customer device in volume from banked base wafers, keeping the wafer bank, test capacity and deliveries in step with the customer's demand, and monitoring yield and field quality.
Volume ramp gate, owned by the Product lifecycle (Volume ramp)Ramp complete gate, owned by the Product lifecycle (Ramp complete)
Keeping the platform and the customer devices built on it supplied: updates to the design kit, process and supply changes notified to customers, and finally the end of the base array, with last-time buys for every customer device that depends on it.
Platform update release gateLast-time buy gate, owned by the Product lifecycle (Last-time buy)Last-time ship gate, owned by the Product lifecycle (Last-time ship)
| Gate array | An older semi-custom chip: a pre-made array of transistors wired for each customer in the metal layers. | The forerunner of the structured ASIC, which also fixes clocks, memories and much of the routing. |
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| Structured ASIC | A chip on a pre-built base array, customised for each design in a few metal or via layers. | Fewer custom masks and a shorter turnaround than a standard cell ASIC; lower unit cost and power than an FPGA. |
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| Base array | The pre-designed, pre-qualified part of a structured ASIC. | Designed and qualified once by the vendor, then shared by every customer design. |
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| Custom layers | The few metal or via layers made for each customer design.For example: Via programmable platforms change only via layers; metal programmable ones also change metal. | The only part of the chip that differs between customers. |
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| Standard cell ASIC | A chip for one customer with every layer made for it. | Higher density and speed than a structured ASIC, but needs a full mask set and a longer schedule. |
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| NRE | The one-time engineering and mask charges for a chip. | Lower for a structured ASIC: less design work, and only custom layer masks. |
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| Mask set | The full set of photomasks for every layer of a chip. | A structured ASIC customer pays for the custom layer masks only. |
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| Metal ECO | A late change made in the metal layers only, on wafers held before them. | An exception on a standard cell chip; routine on a structured ASIC, where every design is made in its upper layers. |
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The structured ASIC lifecycle has two loops. The platform loop runs once per base array: define it, design it with its cell library and design kit, tape out the base layers, bank wafers, then validate and qualify the base. The customer loop runs for every device on that base: take in the design, convert it if it came from an FPGA, implement it, tape out the custom layers, then approve, qualify and produce it.
The vendor owns the platform loop. In the customer loop the customer owns the design and its acceptance, and the vendor owns implementation, manufacture and qualification, usually through a programme manager and a customer ASIC architect.
Compared with the SoC lifecycle, the slow, expensive work is done once in the base and each customer device rides on it, which is why devices can be qualified largely by similarity to the base.
Gates matter in both loops. A mistake in the base reaches every customer. A mistake in a customer design costs a new custom layer tape-out: cheaper than a full respin, but still a lost turnaround.
A dotted underline opens the full definition in the glossary.
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Credible sources, named for further reading. Standards are available from the body that publishes them.