Technology · Process Technology
Forksheet
A nanosheet variant in which a dielectric wall separates the n-device and p-device sheets, letting the n-to-p spacing shrink below what a free-standing gate needs.
It is positioned as a density step between nanosheet and CFET.
- Also known as
- Forksheet FET
- Type
- Technology
- Domain
- Process Technology, Transistor architecture
Notes
The concept originated at imec and is on most public roadmaps for around the 1 nm class generation.
Related terms
- Nanosheet
- CFET
- Cell height
- Dielectric wall
Part of the Process Technology glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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