BSPDN (Backside Power Delivery Network)

Notes

Intel 18A with PowerVia is the first high-volume implementation, with TSMC and Samsung following at their 2 nm class nodes.

Overview

A BSPDN (backside power delivery network) is a way of building a chip so that power and ground reach the transistors from the back of the silicon, through wiring made on the thinned wafer's reverse side, instead of down through the signal wiring above them. Separating power from signals frees routing space on the front and shortens the path power takes, which lowers voltage loss. Intel's PowerVia on its 18A process and TSMC's A16 backside power rail are commercial implementations.

How it works

In a conventional chip, power enters from the package at the top and travels down through the whole stack of metal layers, which imec puts at 15 to 20, getting narrower and more resistive near the transistors. Imec estimates that power wiring takes at least a fifth of routing resources, and the power rails at each standard cell limit how small cells can be.

A BSPDN moves the power network to the other side. In one flow described by imec, the transistors and their front wiring are built as usual, the wafer is flipped and bonded face down to a carrier wafer, and the original silicon is ground, polished and etched away until only a few hundred nanometres remain. Nano through-silicon vias are then patterned from the back to reach the devices, often landing on buried power rails set into the substrate beneath the transistors, and wide, low-resistance backside metal layers complete the network. Intel describes PowerVia as moving coarse-pitch metals and bumps to the back of the die with nano-TSVs in every standard cell.

The extra steps bring new risks: the wafer must be thinned with very little thickness variation, and bonding distorts the wafer, so aligning backside vias to features of standard cell size needs overlay better than 10 nm. Thinning also removes silicon that normally spreads heat, a self-heating question imec is still studying.

Examples

• Intel 18A, which pairs RibbonFET gate-all-around transistors with PowerVia backside power and which Intel says is in high-volume production in the United States.
• Intel's Blue Sky Creek test chip, used on an internal test node to debug PowerVia before combining it with new transistors.
• TSMC A16, which combines nanosheet transistors with a backside power rail.
• Imec's simulation with Arm, which found that buried power rails fed from the backside cut IR drop by about seven times against conventional frontside delivery.

Why it matters

BSPDN changes work for process integration and pathfinding engineers, who must add bonding, thinning and backside patterning, and for standard cell, power integrity and physical design engineers, whose cell layouts, power grids and IR drop analysis assume a different structure. Intel reports lower voltage droop and smaller block area, imec reports lower IR drop, and designers weigh these against added cost and complexity.

Related terms

• PowerVia
• Buried power rail
• nTSV
• Super Power Rail

Where it appears on the Hub

Used on 5 pages of the Hub. In each group, the pages that mention it most come first.