Physical verification

Overview

Physical verification is the set of checks that proves a finished chip layout can be manufactured and matches the circuit it is meant to implement. Its main parts are design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC), together with antenna, density and other foundry checks. Clean or formally waived results against the foundry's approved rule decks are required before tapeout.

How it works

Physical verification tools read the layout, usually in GDSII or OASIS format, and the foundry's rule decks. DRC measures shapes against geometric rules for width, spacing, enclosure and density. LVS extracts the devices and connections from the layout and compares them with the reference netlist, so that a missing contact or an accidental short is found before masks are made. ERC looks for electrical problems such as floating gates, shorted supplies or wells without the right connections. Antenna checks look for long wires that could collect charge during plasma etch and damage gates, and density checks confirm metal and other layers are evenly filled.

On large chips these runs process billions of shapes, so tools work hierarchically and spread the job across many processors. Teams run checks on blocks throughout layout, then on the full chip with all IP, fill and seal ring in place. Each violation is fixed or, if the foundry agrees it is safe, waived with a record.

Physical verification also covers design for manufacturing checks, such as lithography hotspot detection and recommended rules, and the final preparation of the layout data handed to the mask shop.

Examples

• A full-chip DRC run on hundreds of processors overnight before a tapeout.
• An LVS mismatch traced to a missing via in a power connection.
• An antenna violation fixed by adding a protection diode near a gate.
• Metal fill inserted to meet density rules, then checked again.
• A foundry approving a list of waived DRC violations inside a licensed IP block.

Why it matters

A missed physical verification error can make every die fail or yield badly, and it cannot be fixed without new masks, so this step is one of the last and strictest gates before tapeout. Physical verification engineers run and debug the checks, layout and physical design engineers fix the results, and foundries review the final reports.

In the chip lifecycle, physical verification runs continuously during layout and implementation, is completed at full-chip level in signoff, and is the final technical check before the database is released for mask making.

It matters most to: Custom Layout Engineer, EDA R&D Engineer, Physical Verification, ESD and Latch-up Physical Verification Engineer, Physical Signoff Lead, Physical Verification Engineer

Common confusions

Not the same as functional verification

Functional verification checks that the design's logic behaves correctly. Physical verification checks the layout's geometry and connectivity.

Not the same as timing signoff

Timing signoff checks that paths meet their delay requirements. It is a separate part of signoff, though both must pass before tapeout.

Not the same as DRC on its own

DRC is one part of physical verification. LVS, ERC and other checks are also needed.

Sources

1. Calibre Design Solutions (opens in a new tab), Siemens, 2026-10-22
2. Physical Verification (opens in a new tab), Synopsys, 2026-10-22
3. DRC reference (KLayout documentation) (opens in a new tab), KLayout, 2026-10-22
4. Design rule checking (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
5. Layout Versus Schematic (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• DRC
• LVS
• Rule deck
• Signoff

Where it appears on the Hub

Used on 82 pages of the Hub. In each group, the pages that mention it most come first.