Timing closure

Notes

Traditionally the longest tail in a physical design schedule, and the reason tapeout dates slip more often than not.

Overview

Timing closure is the process of changing a chip design until every timing check passes at the target clock frequency in every operating scenario that will be signed off. Engineers track progress with slack, the margin by which each path meets or misses its requirement, and iterate through synthesis, placement, clock tree synthesis, routing and engineering change orders until no negative slack remains. It is less a single step than a goal that runs through the whole implementation phase, and it often decides when a chip can tape out.

How it works

Static timing analysis checks every path between registers against the clock. A setup check asks whether data launched on one clock edge arrives before the next capturing edge; a hold check asks whether new data arrives so early that it corrupts the value still being captured. Slack is the required time minus the arrival time, so negative slack is a violation. Constraints, usually written in SDC, define the clocks, input and output timing and any exceptions.

Engineers clear violations with many levers: resizing gates, inserting buffers, restructuring logic, pulling connected cells closer together, reshaping the floorplan or rebalancing clock skew. For stubborn paths the fix may go back to the RTL, for example by adding a pipeline stage. Every change can create new violations elsewhere, so the flow loops back to timing analysis after each pass, and late fixes on a routed design are made as ECOs.

Closure must hold across many scenarios, combining operating modes with process, voltage, temperature and extraction corners. At advanced nodes the number of scenarios grows, wire resistance and variation matter more, and margins added for variation tighten the targets further. A mismatch between the timing engine used during place and route and the one used for signoff can also stop a design converging, so many flows try to use one consistent engine from synthesis to signoff.

Examples

• A late timing fix in which a tool such as Cadence Tempus ECO resizes cells and inserts buffers on a routed design without redoing placement.
• Adding a pipeline stage to a network-on-chip link after implementation shows that a signal cannot cross the die in a single clock cycle.
• Fixing hold violations that appear only at the fast process corner after setup timing has already been closed at the slow corner.

Why it matters

Physical design engineers, static timing analysis and timing signoff engineers, and the owners of the timing constraints spend much of a project's implementation phase on closure, which Semiconductor Engineering notes can take months. Failing to close means a lower frequency, more power from aggressive fixes, or a slipped tapeout date.

Related terms

• WNS
• TNS
• Functional ECO
• MMMC

Where it appears on the Hub

Used on 24 pages of the Hub. In each group, the pages that mention it most come first.