Acronym · Physical Design & Signoff
MMMC (Multi-Mode Multi-Corner)
An analysis and optimisation setup that evaluates the design simultaneously across several functional modes and several PVT and RC corners, so that fixes for one scenario do not break another.
- Also known as
- Multi mode multi corner
- Type
- Acronym
- Domain
- Physical Design & Signoff, Timing signoff
Notes
Scenario counts in the dozens are normal on modern SoCs, making MMMC the dominant driver of signoff compute cost.
Overview
MMMC, short for multi-mode multi-corner, is the practice of analysing and optimising a chip's timing across many combinations of operating modes and process, voltage, temperature and interconnect corners together, rather than one combination at a time. Each combination of a mode, a delay corner, a parasitic corner and a cell library is called a view, and the design must meet timing in every view that matters. The same idea is also written MCMM, for multi-corner multi-mode.
How it works
A mode is a way the chip operates, such as one of its functional modes or a test mode, and each has its own set of timing constraints. A corner fixes the physical conditions: transistor process (fast or slow), supply voltage, temperature, and an interconnect corner from extraction, such as worst capacitance or worst resistance and capacitance. Each view is then checked for setup, hold or both.
The number of views grows quickly at advanced nodes. An EE Journal article from 2012 worked through a 28 nm example in which the full set of conditions gave 100 corners; trimming that to 32 and adding three test modes and five functional modes still produced more than 250 views, which engineering judgement could cut to about 100. A Cadence patent mentions configurations of 1,000 or more views.
Analysing every view separately is slow, so tools take two broad approaches. One runs views in parallel across a compute farm and merges the results; the other analyses many views in one run, sharing the parts of the timing graph that do not differ between them. Implementation tools usually optimise against only a subset of the views, with full coverage checked at signoff. Replacing views with extra timing derates is cheaper but adds pessimism that can cost area and power.
Examples
- The 28 nm case in EE Journal, where 32 corners combined with eight modes gave more than 250 timing views before reduction.
- A scan test mode analysed with its own clocks and constraints alongside the functional modes in the same run.
- Hold fixes made without physical awareness that degraded setup timing, an effect EE Journal illustrates for signoff changes.
- Distributing hundreds of views across many machines and merging their results into one signoff session, as described in a Cadence patent.
Why it matters
Most timing fixes help in one view and hurt in another: speeding a path for setup at a slow corner can break hold at a fast one. MMMC lets static timing and physical design engineers see these interactions at once, and timing signoff engineers use it to show the design works in every mode and corner the product will meet.
In the chip lifecycle, the mode and corner list is agreed early in implementation from the product's operating modes and the foundry's signoff corners, then used through synthesis, place and route, signoff and every late timing change before tapeout.
It matters most to: Physical Design Engineer, Static Timing Analysis Engineer, Timing Engine Developer, Timing Signoff Engineer
Common confusions
- Not the same as PVT corner
- A PVT corner is one set of process, voltage and temperature conditions. MMMC is the framework that combines many corners with many modes.
- Not the same as timing derates
- Derates add margin to delays within a view to cover variation or effects not analysed. Using derates in place of additional views is cheaper but more pessimistic.
Sources
- How to Close Timing with Hundreds of Multi-Mode/Multi-Corner Views (6 December 2012) (opens in a new tab), EE Journal, 2026-10-22
- US9633159B1: Method and system for performing distributed timing signoff and optimization (opens in a new tab), Google Patents (patent assigned to Cadence Design Systems, Inc.), 2026-10-22
- US10990733B1: Shared timing graph propagation for multi-mode multi-corner static timing analysis (opens in a new tab), Google Patents (patent assigned to Cadence Design Systems, Inc.), 2026-10-22
Related terms
Part of the Physical Design & Signoff glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 4 pages of the Hub. In each group, the pages that mention it most come first.
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