Glitch

Notes

Glitch on a clock or asynchronous reset is far more dangerous than on a combinational net because it can latch permanently.

Overview

A glitch, in chip signal integrity, is a short unwanted voltage bump on a net that should be holding a steady logic value, induced through coupling capacitance when a neighbouring wire switches. Static noise analysis looks for glitches large enough for the receiving gate to treat them as a real transition, because a glitch that is captured by a register, or that reaches a clock or reset pin, can corrupt the state of the chip. The word is also used loosely for any brief spurious pulse.

How it works

The switching wire is called the aggressor and the quiet wire the victim. When the aggressor changes state, charge couples across the capacitance between the two wires and pushes the victim briefly up or down. How big the bump gets depends on how much of the victim's capacitance is to its neighbours, how strongly the victim's driver holds the net, how fast the aggressor edge is, and whether several aggressors switch at once. This is the same coupling that causes crosstalk delay, but there the victim is itself switching and the effect is a change in timing rather than a pulse.

Noise analysis tools work from the routed layout with extracted parasitics. For each victim they estimate the injected bump, add noise propagated through the victim's own driver, and compare the result with what the receiving gate can tolerate. Early checks used a simple height threshold, which flagged many tall but very narrow spikes that do no harm; current tools judge a glitch by how the receiving cell actually responds, using noise data in the cell libraries.

Typical fixes are upsizing the victim's driver, inserting buffers on the victim net, or separating or shielding the wires.

Examples

• Static noise analysis flagging a bump on a quiet reset line routed beside a wide bus whose bits switch together.
• A glitch on a register's clock or asynchronous reset pin, treated as more serious than one on a data input because it can change the register's state directly.
• A signoff engineering change order that upsizes the driver of a victim net so it holds its quiet value more firmly.
• A small glitch propagated through a gate combining with fresh crosstalk on that gate's output to produce a failure neither would cause alone.

Why it matters

Timing signoff and signal integrity engineers run glitch analysis on every advanced digital design, and physical design engineers fix the violations it reports. A missed glitch is hard to find in silicon: the failure may appear only with a particular switching pattern and look like a random logic error.

Related terms

• Crosstalk
• Shielding

Where it appears on the Hub

Used on 8 pages of the Hub. In each group, the pages that mention it most come first.