Derating

Notes

Derates are a direct performance tax, so teams push from flat OCV toward POCV specifically to reclaim that margin.

Overview

Derating, in static timing analysis, is the practice of scaling calculated cell and wire delays up or down by a factor so that timing checks allow for on-chip variation and other effects that the nominal delays do not capture. A late derate makes a path slower than calculated and an early derate makes it faster, and the tool applies each to whichever side of a check makes the result more pessimistic. Derating is one form of timing margin, used alongside clock uncertainty and the choice of process corners.

How it works

A setup check compares the slowest arrival of data with the earliest arrival of the capturing clock, and a hold check does the reverse. Derating builds on this. For setup, the launch clock and data path receive a late derate, for example 1.05, and the capture clock path an early derate, for example 0.95; for hold the roles swap. In the open-source OpenSTA timer, the set_timing_derate command takes an early or late factor and can be limited to clock or data paths and to cell or net delays.

A single flat derate for the whole chip is simple but crude. It is too optimistic for short paths and too pessimistic for long ones, because random variation partly cancels out along a long chain of gates. Advanced OCV (AOCV) therefore looks up derates by path depth and distance, and parametric OCV (POCV) gives each cell its own statistical spread, or sigma, and combines the sigmas along a path instead of simply adding margins. For finer accuracy, libraries carry sigma tables in the Liberty variation format (LVF), produced by Monte Carlo characterisation.

The launch and capture clocks usually share the first part of the clock tree, and a cell on that shared section cannot be fast and slow at once, so timing reports typically include a clock reconvergence pessimism adjustment that gives that margin back. Choosing derates is a trade-off: too much wastes area and power on unnecessary fixes, too little lets real silicon miss its frequency.

Examples

• AOCV tables that give a short path a larger derate than a deep one, because variation along the deep path partly averages out.
• POCV analysis with LVF libraries on an advanced FinFET process, reporting slack at three sigma.
• A derate applied only to net delays with OpenSTA's set_timing_derate command, adding margin for wire delay without touching cell delays.

Why it matters

Static timing and timing signoff engineers choose and apply derates within the signoff methodology agreed for a process, while library characterisation engineers produce the variation data behind POCV and LVF.

Related terms

• OCV
• AOCV
• POCV
• CRPR
• Guardband
• Margin

Where it appears on the Hub

Used on 17 pages of the Hub. In each group, the pages that mention it most come first.