Term · Physical Design & Signoff
Timing arc
A characterised delay or constraint relationship in a library cell between two pins, such as input to output propagation, or a setup or hold requirement between data and clock.
STA builds path delays by chaining arcs.
- Also known as
- Delay arc, Cell arc
- Type
- Term
- Domain
- Physical Design & Signoff, Timing signoff
Notes
Arcs are indexed by input transition and output load, which is why slew and capacitance discipline drives timing accuracy.
Related terms
Part of the Physical Design & Signoff glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
No other page of the Hub uses this term yet.
Suggest an improvement
Suggest an improvement to this entry
A clearer definition, an example, a correction or a source an editor can check. Editors review every suggestion before the entry changes.
Last reviewed: not yet reviewed in depth. Entry last updated . The full glossary