Process · Physical Design & Signoff
Power gating
Cutting supply to an idle block using header or footer switch cells so that its leakage falls to near zero, at the cost of state loss, wake-up latency and inrush current when the block is restored.
- Also known as
- MTCMOS, Power shutoff, Power shut-off, PSO
- Type
- Process
- Domain
- Physical Design & Signoff, Power analysis
- Also relevant to
- Design & Architecture
Notes
Wake-up inrush is itself a power integrity problem, which is why switch cells are turned on in a staged daisy chain.
Overview
Power gating is a low-power design technique that switches off the supply to a block of a chip while the block is idle, using power switch cells, so that the block stops leaking current as well as switching. It typically gives the largest saving of the common low-power techniques. The price is that the block loses its state unless retention is added, takes time to wake up, and needs carefully controlled switching, isolation and restore sequences.
How it works
The chip is divided into power domains, and each domain that can be turned off is fed through switch cells placed in its supply path, either PMOS header switches on the supply side or NMOS footer switches on the ground side. When the switches open, both dynamic and leakage power in that domain fall to almost nothing for as long as it stays off, which is why power gating saves more than clock gating, which stops only switching activity.
Several supporting pieces are needed. Isolation cells clamp the outputs of a switched-off domain to known values so that they do not disturb the blocks that remain on. Retention registers, where used, save some or all of the domain's state before power down and restore it afterwards, so the block can resume quickly instead of restarting from reset. A power management unit, kept in an always-on domain, drives the switch, isolation and save and restore signals in the correct order; getting this order wrong is a classic source of bugs.
The power intent, meaning the domains, switches, isolation and retention, is written in UPF, defined by IEEE 1801, and the same description guides synthesis, placement of the switches, verification and signoff. Costs include the area and IR drop of the switches, the energy and time needed to enter and leave the off state, and the rush current drawn when a large block powers up, which is why switches are usually turned on in stages.
Examples
- A mobile SoC that switches off a graphics or media block whenever it is not in use.
- A block that keeps its configuration in retention registers while powered down, so it wakes without reprogramming.
- An always-on domain holding the power controller and wake-up logic while the rest of the chip is off.
- Power switch cells inserted and placed during physical implementation according to the UPF.
Why it matters
In battery-powered and always-connected products, leakage while idle can dominate energy use, and power gating is one of the few techniques that removes it. Low-power design and implementation engineers, UPF power intent engineers, power architects and low-power verification engineers all work on it, and mistakes can leave a chip unable to wake up.
Related terms
Part of the Physical Design & Signoff glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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