Utilisation

Notes

Typical starting targets run 60 to 80 percent, lower for congested or high-frequency blocks.

Overview

Utilisation, in chip physical design, is the share of the placeable core area that is occupied by standard cells and macros, usually quoted as a percentage. Engineers choose a target utilisation when sizing a floorplan and then watch the real figure climb as placement and optimisation add buffers and enlarge cells. The word means something different elsewhere in the industry, where it describes how busy a processor or a fab tool is.

How it works

The sum is simple: add up the area of every placed instance and divide it by the area of the core, the region inside the I/O ring where rows of cell sites are laid out. Some teams include macros in the count, while others report standard cell utilisation over the area left once macros and blockages are removed, so a quoted figure should say which it uses. The OpenROAD floorplan command shows the link directly: it can work out the core size from the total cell area, a chosen utilisation and an aspect ratio.

A lower target leaves room for what arrives later: buffers added to fix timing, upsized cells, clock tree cells, spare cells and, above all, routing tracks. A higher target shrinks the die and the cost of each chip, but packs cells so tightly that wires have nowhere to go, leading to congestion, detours and harder timing closure.

Placers also work with local density, the utilisation of small bins across the core. OpenROAD's global placer, for example, defaults to a target density of 70 per cent, and its routability-driven mode inflates cells in congested areas. A block can meet its overall target and still contain hot spots that will not route, so engineers study congestion maps as well as the single number.

Examples

• A block floorplanned from its synthesised cell area with a 70 per cent utilisation target and an aspect ratio of 1.0, using the OpenROAD initialize_floorplan command.
• A memory-heavy block in which large SRAM macros fill most of the core, so standard cell utilisation is reported over the area left between them.
• A congestion map showing a local hot spot around a wide multiplexer, relieved by spreading cells in that region rather than enlarging the whole block.
• A cost-sensitive consumer chip whose die size estimate assumes a high utilisation and accepts a longer routing and timing closure effort in return.

Why it matters

Floorplanning and place-and-route engineers set utilisation targets early and defend them through implementation, because die area drives wafer cost and dies per wafer, while routability and timing margin drive the schedule. A target that proves too aggressive can force a late floorplan change.

Related terms

• Floorplan
• Congestion
• Die size
• Core area

Where it appears on the Hub

Used on 32 pages of the Hub. In each group, the pages that mention it most come first.