Critical path

Notes

Real closure is usually a wall of near-critical paths rather than one path, which is why TNS-driven effort beats chasing the top violator.

Overview

The critical path is the timing path in a digital circuit with the least slack, usually the slowest chain of logic between two registers, and it sets the highest clock frequency the design can run at. Static timing analysis finds it by adding up cell and wire delays along every path and comparing each total with what the clock allows. Optimisation effort goes to it first, and once it is fixed another path becomes critical in its place.

How it works

A timing path starts where data is launched, at an input port or a register's clock pin, passes through combinational logic, and ends where data is captured, at a register's data input or an output port. For each path the timing tool computes when the data arrives and when it is required, which depends on the clock period, the clock's arrival at each register and the capturing register's setup time. Slack is the required time minus the arrival time: positive slack means the path has margin, negative slack means it is too slow. The critical path is the one with the most negative, or least positive, slack.

The critical path depends on conditions. Timing is checked at several process, voltage and temperature corners, and the slowest path at one corner may not be the slowest at another. Designs also have path groups, such as register to register, input to register and paths through memories, each with its own worst path. In practice designers watch the spread of slack across many near-critical paths, because fixing only the single worst one often exposes others just behind it.

Common fixes include upsizing cells, adding or removing buffers, moving cells closer together, using faster but leakier transistors, restructuring logic, adding a pipeline stage or relaxing the frequency target. Each costs area, power, latency or schedule.

Examples

• A timing report after routing that lists the worst path in each path group, with its slack at every corner.
• A wide adder whose carry chain limits frequency until it is replaced by a faster adder structure.
• An extra pipeline register added to a processor's execution stage so that a path no longer limits the clock rate.
• OpenSTA used to report timing checks from, through and to chosen points to study the paths nearest to failing.

Why it matters

Logic designers, synthesis engineers, physical design engineers and timing signoff engineers all work on the critical path, because its delay decides the chip's frequency, or how much voltage it needs to reach a target frequency. Architects shape it too, through pipeline depth and where registers sit.

Related terms

• WNS
• Slack
• Path group
• Timing-driven placement
• Long pole
• Slip

Where it appears on the Hub

Used on 14 pages of the Hub. In each group, the pages that mention it most come first.