Indicative Lifecycle Timelines

End to end, by lifecycle and class

One shared scale in months across every lifecycle. Each row is a class with its cited range; the labels give each source's own figure.

• Product lifecycleWork in progress

  • Light change (effort classes 1 and 2)
    No published source yet
  • Silicon change (effort classes 3 and 4)
    No published source yet
  • New platform (effort class 5)
    No published source yet

• SoC lifecycleWork in progress

  • Derivative SoC
    No published source yet
  • Mainstream SoC
    12 to 36 months ^{[1, Statements on the customer chip design cycle and on time from initial development of new products to licence revenue]}
  • Large or leading-edge SoC
    160 weeks ^{[2, Statement of the current custom defence ASIC design time and the programme target]}

• Soft IP lifecycleWork in progress

  • Configuration or update of an existing block
    No published source yet
  • New digital block
    12 to 36 months ^{[1, Statements on the customer chip design cycle and on time from initial development of new products to licence revenue]}
  • New complex IP product line
    36 to 48 months ^{[1, Statements on the customer chip design cycle and on time from initial development of new products to licence revenue]}

• Hard IP lifecycleWork in progress

  • Port or update of an existing macro
    No published source yet
  • New macro on a mature process
    No published source yet
  • New macro on a new process
    No published source yet

• Up to the cited minimum
• Minimum to maximum
• No published source yet