The views of the macro characterised from the signed-off layout across all agreed corners: abstract, timing and power models, noise and signal integrity models, behavioural and circuit models, and the test views.
Design data Work product in the SoC and full-chip lifecycle and the Hard IP lifecycle
Integrators sign off their chips with these views, so errors in them become errors in the integrator's chip. Releasing them before silicon lets SoC teams complete their physical sign-off with the macro included.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.