Chip lifecycle / Work products / Timing models

Timing models

Timing views of an IP block, so the SoC can check timing without the block's full detail.

Model Work product in the SoC and full-chip lifecycle and the Soft IP lifecycle

Why it exists and what it decides

They let the SoC check timing at and around an IP block without loading its full detail, which is essential for full-chip timing sign-off. If they do not match the IP layout or cover all corners, chip timing sign-off is wrong and silicon may fail at speed.

Decisions it informs

Whether IP timing is correctly represented in full-chip sign-off
Which corners and modes the IP supports
Whether timing model and layout versions match

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