Chip lifecycle / Hand-off map
Lifecycle Hand-off Map
Each arrow is work one function passes to another: forward hand-offs move work on through the lifecycle, and feedback hand-offs (↩) carry findings back, such as bug reports, silicon escapes and change requests. Open one to see the work products, the maturity expected, the gate it happens at, how the receiver checks it, and what goes wrong when the hand-off is weak.
Function by function
Rows hand off to columns. On a narrow screen the grid scrolls inside its box, with the function names kept in view.
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Every hand-off, by lifecycle (205)
Every page is listed by name. Each one opens with its summary; the full page is for registered members.
Soft IP and SoC lifecycles (52)
- Product management to Architecture and specification
- Architecture and specification to RTL design
- Architecture and specification to Functional verification
- Architecture and specification to Design for test
- Architecture and specification to Physical design and sign-off
- IP design to IP integration
- IP quality and release to IP integration
- IP verification to Functional verification
- IP integration to IP design
- IP integration to IP quality and release
- Physical design and sign-off to IP design
- RTL design to Functional verification
- Functional verification to RTL design
- Functional verification to Architecture and specification
- RTL design to Architecture and specification
- RTL design to Design for test
- RTL design to Physical design and sign-off
- Physical design and sign-off to RTL design
- Physical design and sign-off to Functional verification
- Design for test to Physical design and sign-off
- Silicon validation and bring-up to IP quality and release
- Design for test to Functional verification
- IP quality and release to RTL design
- IP quality and release to Functional verification
- Physical design and sign-off to Design for test
- Architecture and specification to System modelling and virtual prototyping
- Architecture and specification to Performance and power-performance analysis
- Performance and power-performance analysis to Architecture and specification
- System modelling and virtual prototyping to RTL design
- Performance and power-performance analysis to RTL design
- RTL design to Performance and power-performance analysis
- System modelling and virtual prototyping to Firmware and software
- System modelling and virtual prototyping to Functional verification
- RTL design to Emulation
- RTL design to FPGA prototyping
- Emulation to Firmware and software
- FPGA prototyping to Firmware and software
- Emulation to Functional verification
- Emulation to RTL design
- Emulation to Performance and power-performance analysis
- FPGA prototyping to Functional verification
- FPGA prototyping to RTL design
- Emulation to Silicon validation and bring-up
- FPGA prototyping to Silicon validation and bring-up
- Silicon validation and bring-up to Performance and power-performance analysis
- Product management to Performance and power-performance analysis
- System modelling and virtual prototyping to Architecture and specification
- Functional verification to Emulation
- Performance and power-performance analysis to Emulation
- Performance and power-performance analysis to Product management
- System modelling and virtual prototyping to IP integration
- FPGA prototyping to Product management
SoC lifecycle (104)
- Architecture and specification to Firmware and software
- Architecture and specification to Packaging and test
- Architecture and specification to Foundry and process
- Architecture and specification to IP integration
- IP integration to Physical design and sign-off
- IP integration to Design for test
- IP integration to Third-party IP intake
- Silicon validation and bring-up to IP integration
- IP integration to RTL design
- IP integration to Functional verification
- Functional verification to Silicon validation and bring-up
- Design for test to Packaging and test
- Packaging and test to Design for test
- Foundry and process to Physical design and sign-off
- Physical design and sign-off to Foundry and process
- Physical design and sign-off to Packaging and test
- Foundry and process to Packaging and test
- Foundry and process to Manufacturing and yield
- Manufacturing and yield to Foundry and process
- Packaging and test to Silicon validation and bring-up
- Packaging and test to Quality and reliability
- Packaging and test to Manufacturing and yield
- Quality and reliability to Packaging and test
- Firmware and software to Silicon validation and bring-up
- Silicon validation and bring-up to Firmware and software
- Silicon validation and bring-up to Functional verification
- Silicon validation and bring-up to RTL design
- Silicon validation and bring-up to Physical design and sign-off
- Silicon validation and bring-up to Quality and reliability
- Silicon validation and bring-up to Product management
- Quality and reliability to Product management
- Quality and reliability to Manufacturing and yield
- Manufacturing and yield to Product management
- Architecture and specification to Product management
- Architecture and specification to Quality and reliability
- Architecture and specification to Silicon validation and bring-up
- Firmware and software to Architecture and specification
- IP integration to Architecture and specification
- Physical design and sign-off to Architecture and specification
- Silicon validation and bring-up to Architecture and specification
- Product management to Firmware and software
- Product management to Manufacturing and yield
- Product management to Quality and reliability
- Product management to Silicon validation and bring-up
- IP integration to Product management
- Design for test to Product management
- Functional verification to Product management
- Packaging and test to Product management
- Physical design and sign-off to Product management
- Firmware and software to Product management
- Functional verification to Design for test
- Design for test to RTL design
- Design for test to Silicon validation and bring-up
- Silicon validation and bring-up to Design for test
- Design for test to Manufacturing and yield
- Manufacturing and yield to Design for test
- Design for test to Quality and reliability
- Foundry and process to Design for test
- Functional verification to Physical design and sign-off
- RTL design to IP integration
- RTL design to Firmware and software
- Firmware and software to RTL design
- Firmware and software to Functional verification
- RTL design to Quality and reliability
- Quality and reliability to RTL design
- Quality and reliability to Functional verification
- RTL design to Silicon validation and bring-up
- Packaging and test to Physical design and sign-off
- Physical design and sign-off to Quality and reliability
- Quality and reliability to Physical design and sign-off
- Physical design and sign-off to Silicon validation and bring-up
- Manufacturing and yield to Physical design and sign-off
- Foundry and process to Quality and reliability
- Quality and reliability to Foundry and process
- Foundry and process to Silicon validation and bring-up
- Silicon validation and bring-up to Foundry and process
- Silicon validation and bring-up to Manufacturing and yield
- Foundry and process to Product management
- Silicon validation and bring-up to Packaging and test
- Quality and reliability to Silicon validation and bring-up
- Quality and reliability to Firmware and software
- Manufacturing and yield to Packaging and test
- Manufacturing and yield to Quality and reliability
- IP integration to Silicon validation and bring-up
- System modelling and virtual prototyping to Performance and power-performance analysis
- System modelling and virtual prototyping to Emulation
- Architecture and specification to Emulation
- Performance and power-performance analysis to System modelling and virtual prototyping
- Firmware and software to System modelling and virtual prototyping
- Firmware and software to Performance and power-performance analysis
- Firmware and software to Emulation
- Firmware and software to FPGA prototyping
- Functional verification to FPGA prototyping
- Functional verification to System modelling and virtual prototyping
- RTL design to System modelling and virtual prototyping
- Emulation to System modelling and virtual prototyping
- Performance and power-performance analysis to Functional verification
- Performance and power-performance analysis to Physical design and sign-off
- Physical design and sign-off to Performance and power-performance analysis
- Emulation to Physical design and sign-off
- Performance and power-performance analysis to Silicon validation and bring-up
- Silicon validation and bring-up to Emulation
- Silicon validation and bring-up to FPGA prototyping
- IP integration to System modelling and virtual prototyping
Soft IP lifecycle (49)
- Architecture and specification to IP design
- Architecture and specification to IP verification
- Architecture and specification to Third-party IP intake
- IP design to IP verification
- IP design to Design for test
- IP design to Physical design and sign-off
- IP verification to IP design
- IP verification to IP quality and release
- Design for test to IP quality and release
- Physical design and sign-off to IP quality and release
- Third-party IP intake to IP quality and release
- IP quality and release to Third-party IP intake
- IP design to IP quality and release
- IP quality and release to IP design
- Architecture and specification to IP quality and release
- IP design to Architecture and specification
- IP verification to Architecture and specification
- Product management to IP integration
- Product management to IP design
- Product management to IP quality and release
- Product management to Third-party IP intake
- Third-party IP intake to Product management
- IP verification to Product management
- IP design to Product management
- IP quality and release to Product management
- Design for test to IP design
- Functional verification to IP design
- Functional verification to IP verification
- Functional verification to IP quality and release
- IP design to RTL design
- RTL design to IP design
- RTL design to IP verification
- RTL design to IP quality and release
- IP design to FPGA prototyping
- FPGA prototyping to IP design
- System modelling and virtual prototyping to IP quality and release
- Product management to System modelling and virtual prototyping
- System modelling and virtual prototyping to IP design
- IP design to System modelling and virtual prototyping
- System modelling and virtual prototyping to IP verification
- IP verification to System modelling and virtual prototyping
- IP verification to Performance and power-performance analysis
- Performance and power-performance analysis to IP verification
- Performance and power-performance analysis to IP design
- IP design to Performance and power-performance analysis
- Performance and power-performance analysis to IP quality and release
- FPGA prototyping to IP verification
- FPGA prototyping to IP quality and release
- Emulation to IP design