Skip to main content
Chip lifecycle / Hand-off map / Design for test to RTL design

Design for test to RTL design

DFT reports scan rule violations, untestable logic, test point requests and test mode issues traced to the RTL, so design fixes them while the RTL can still change.

Work products passed
  • Scan and BIST logic
  • DFT architecture
  • Bug reports

Register or sign in to read on

The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.