News from October 2026
665 stories of semiconductor news published on the Hub in October 2026, newest first and grouped by day (UTC). Each headline opens the story's page on the Hub, with a summary and a link to the original report.
Showing 201 to 250 of 665 stories.
Wednesday 28 October 202681 stories
SK hynix-owned Solidigm is plotting a new $45 billion flash memory factory for the US, report claimsMarkets & Policy · Tom's Hardware · Summary
Image: Tom's Hardware (opens in a new tab) Solidigm, an American subsidiary of SK hynix, is in discussions about potentially investing $45 billion in a new flash chip factory that would be built in the United States.
North American EMS Orders Climb Despite Lower September ShipmentsMarkets & Policy · Global Electronics Association (formerly IPC) · Summary
Image: Global Electronics Association (formerly IPC) (opens in a new tab) North American EMS Orders Climb Despite Lower September Shipments 431279_sandyge… Oct 28, 2026 Oct 28, 2026 The Global Electronics Association releases EMS industry results for September 2026 The Global Electronics Association announced today the September 2026 findings from its North American Electronics Manufacturing Services (EMS) Statistical Program.
The book-to-bill ratio stands at 1.68. Total North American EMS shipments in September 2026 were down 10.8% compared to the same month last ye…
ScaleFlux Appoints Greg Ernst as Chief Business Officer to Drive Global Growth in AI InfrastructureMarkets & Policy · PR Newswire · Summary
Image: PR Newswire (opens in a new tab) Former Intel Chief Revenue Officer brings 27 years of experience and deep relationships across hyperscaler, OEM, and ODM customers MILPITAS, Calif., Oct. 28, 2026 /PRNewswire/ -- ScaleFlux, a leader in storage and memory silicon solutions for AI infrastructure, today announced the...
Intel gets tax breaks while local authorities lose revenue, claims policy orgMarkets & Policy · The Register · Summary
Image: The Register (opens in a new tab) Report accuses corp of getting subsidies for its fabs from Oregon and New Mexico that deprive those states of vital funds
Retro Gaming Console on RV32IM CPU (DE0 Nano FPGA)Design & IP · r/chipdesign · Summary
Image: r/chipdesign (opens in a new tab) Can it run DOOM? This is an entry for the Hackaday Retrocomputing Challenge by DigiKey, brought up on the Intel Cyclone IV (Terasic DE0-Nano) FPGA, building on the previous CPU work I put my dual-issue RV32IM superscalar CPU, with custom UART, I2C, and FIFO IPs, on an FPGA and built a retro system around it.
A launcher lets you choose between DOOM, a Wolfenstein-style raycaster, and custom games such as Snake, 2048, Tetris, Minesweeper, and Flappy Bird. It also runs classic 8-bit software in a …
Microchip adds LX-820 Quartz Oscillator to L-Series for LEO appsMarkets & Policy · Electronics Weekly · Summary
Image: Electronics Weekly (opens in a new tab) Microchip is adding the LX-820 Radiation-Tolerant Quartz Oscillator to its L-Series of timing devices. The part is designed for Low Earth Orbit (LEO) and other space applications.
The L-Series is […] The post Microchip adds LX-820 Quartz Oscillator to L-Series for LEO apps appeared first on Electronics Weekly.
OrcaRouter Launches Orca Connect, Turning Any Local GPU into a Free, Globally Accessible AI APIDesign & IP · PR Newswire · Summary
Image: PR Newswire (opens in a new tab) New infrastructure bridges local and cloud AI inference, allowing developers to securely access, share, and scale their own GPU resources without port forwarding or complex configuration. SAN FRANCISCO, Oct. 28, 2026 /PRNewswire/ -- Continuum AI today announced the launch of Orca Connect,...
Standalone Nvidia Vera CPUs land in Oracle Cloud's multi-gigawatt deployment — our independent benchmarking of a local server reveals Vera's massive memory bandwidth lead over dual Xeon 6 serverDesign & IP · Tom's Hardware · Summary
Image: Tom's Hardware (opens in a new tab) Nvidia’s Vera CPU is now generally available on Oracle’s OCI Superclusters, a win for Nvidia as it moves past NVL72 to a standalone Vera deployment at a major hyperscaler.
Save $249 on 32GB of DDR5 with this 9800X3D parts bundleMarkets & Policy · Tom's Hardware · Summary
Image: Tom's Hardware (opens in a new tab) Save $248.99 on this AMD Ryzen 7 9800X3D bundle at Newegg with an MSI MAG X870E Tomahawk Max Wifi motherboard and 32GB of DDR5-6000 RAM, now just $1,094.99.
Nvidia RTX GPU vendor Palit denies its Galax factory has closed due to a shortage of chipsDesign & IP · Tom's Hardware · Summary
Image: Tom's Hardware (opens in a new tab) Palit denies news that Galax is going out of production.
Google alters its cloud playbook, enlisting partners to sell more AI chipsDesign & IP · CNBC Technology · Summary
Image: CNBC Technology (opens in a new tab) Google is opening its TPU business beyond its own cloud as custom chips become a bigger engine for growth.
Ceva’s Next-Generation NeuPro Brings a Unified AI Platform from Sensors to InfrastructureDesign & IP · SemiWiki Forums · Summary
Image: SemiWiki Forums (opens in a new tab) Ceva is expanding the reach of its neural processing technology with a next-generation NeuPro portfolio designed to serve everything from always-on sensors to AI infrastructure.
The announcement introduces four NPU families sharing a common architecture and unified software stack, giving semiconductor developers a consistent… Read More The post Ceva’s Next-Generation NeuPro Brings a Unified AI Platform from Sensors to Infrastructure appeared first on SemiWiki.
Ceva Unveils Next-Generation NeuPro NPU Portfolio and Announces Expansion into AI InfrastructureDesign & IP · PR Newswire · Summary
Image: PR Newswire (opens in a new tab) A common architecture and unified software stack span Physical AI applications from always-on sensors to AI infrastructure, delivering up to 2X higher AI throughput per mm² and 50% better energy efficiency for the latest multimodal, generative and agentic AI workloads ROCKVILLE, Md., Oct....
Huawei’s Tau Scaling Law roll-out reaches base stations in blow to US chip curbsMarkets & Policy · South China Morning Post - Tech · Summary
Huawei Technologies is already integrating elements of the Tau Scaling Law – a new chip design principle that helps the company overcome US export controls – into its wireless communications network, as it pushes for broader adoption across its products.
The Chinese tech giant is using the “time compression” concept based on its Tau Scaling Law in its next-generation wireless base stations, according to a company statement released on Wednesday, and the new design is already delivering tangible…
Advanced Packaging Process Control Through Full-Field Wafer Shape Using WFPIPackaging & Test · Semiconductor Digest · Summary
Image: Semiconductor Digest (opens in a new tab) Backside power delivery networks and HBM stacks depend on wafer bonding with tight pitches and overlay budgets, and even small bonding-induced distortions can turn into yield loss in downstream CMP, lithography and stacking.
Traditional metrology often can’t deliver fast, full-wafer, non-destructive measurements at the speed high-volume manufacturing requires. The post Advanced Packaging Process Control Through Full-Field Wafer Shape Using WFPI appeared first on Semiconductor Digest.
Enabling Next-Generation Plasma Dicing with Ultrasonic Spray Coating and Digital LithographyEquipment & Materials · Semiconductor Digest · Summary
Image: Semiconductor Digest (opens in a new tab) Plasma dicing offers clear advantages over saw and laser singulation for thin wafers, hybrid bonding and HBM: throughput that doesn’t depend on die count, dicing streets as narrow as 5 µm and less mechanical stress.
But bumps, copper pillars and cavities make it hard to protect the die surface during plasma etching, and conventional spin coating struggles to cover that topography. The post Enabling Next-Generation Plasma Dicing with Ultrasonic Spray Coating and Digital Lithography appeared firs…
From Lab to Fab: The Rise of HiPIMS in Semiconductor ManufacturingFoundry & Manufacturing · Semiconductor Digest · Summary
Image: Semiconductor Digest (opens in a new tab) High-power impulse magnetron sputtering (HiPIMS) produces denser, better-adhering films than conventional sputtering, but scaling it to 200mm-plus substrates and inline production takes more than turning up the power.
Authors from VON ARDENNE describe the engineering investment needed to move the technique from the lab into high-volume manufacturing. The post From Lab to Fab: The Rise of HiPIMS in Semiconductor Manufacturing appeared first on Semiconductor Digest.
Wafer-Level Burn-In for Improved WBG Device ReliabilityPackaging & Test · Power Electronics News · Summary
Wafer-level burn-in screens SiC and GaN devices for infant mortality failures before packaging, improving module yields and reliability. The post Wafer-Level Burn-In for Improved WBG Device Reliability appeared first on Power Electronics News.
IT vendor lists massive $60 million AI supercomputer on eBay with 300 racks of decommissioned GPUsDesign & IP · Tom's Hardware · Summary
Image: Tom's Hardware (opens in a new tab) Someone listed a massive 300-rack AI supercomputer on eBay for $59.7M. Packed with 9,600 A100 GPUs and 4,200 EPYC CPUs, it even ships for free.
MetaOptics Adopts Share Buy-Back Mandate to Enhance Capital Management Flexibility as the Group Advances Commercial Deliveries and Next-Generation Metalens MilestonesMarkets & Policy · PR Newswire · Summary
SINGAPORE, Oct. 28, 2026 /PRNewswire/ -- MetaOptics Ltd (Catalist: 9MT) ("MetaOptics" or the "Company", and together with its subsidiaries, the "Group"), a leading-edge semiconductor optics company, today announced the strong support received from shareholders at the extraordinary general...
Intel Wants a Quantum Business, Classiq Could Help Build OneMarkets & Policy · EE Times · Summary
Image: EE Times (opens in a new tab) After years of hardware research, Intel plans to acquire a software platform that connects quantum developers with enterprise users. The post Intel Wants a Quantum Business, Classiq Could Help Build One appeared first on EE Times.
Infineon and Enphase develop 900 V GaN switches for AI data centresEquipment & Materials · eeNews Europe · Summary
Image: eeNews Europe (opens in a new tab) Infineon Technologies is supplying Enphase Energy with 900 V gallium nitride (GaN) bidirectional switches for solid-state transformers used in AI data centre power systems.
The companies claim the CoolGaN devices are the world’s first monolithic GaN bidirectional switches at this voltage rating, extending the technology into higher-voltage power conversion applications. For eeNews Europe readers working […] The post Infineon and Enphase develop 900 V GaN switches for AI data centres appeared fi…
Blog Review: Oct. 28Markets & Policy · Semiconductor Engineering · Summary
Image: Semiconductor Engineering (opens in a new tab) STCO for heterogeneous design; physical AI interactions; signing off AI-generated designs; workload profile analysis. The post Blog Review: Oct. 28 appeared first on Semiconductor Engineering.
How Much Can Semiconductor Models Hide?Packaging & Test · Semiconductor Engineering · Summary
Image: Semiconductor Engineering (opens in a new tab) Advanced packaging requires models to cross company boundaries without exposing proprietary processes, but hiding too much can make the prediction break down. The post How Much Can Semiconductor Models Hide? appeared first on Semiconductor Engineering.
Planning Your AI Design Journey In RF EDAEDA & Tools · Semiconductor Engineering · Summary
Image: Semiconductor Engineering (opens in a new tab) Agentic solutions for RF design. The post Planning Your AI Design Journey In RF EDA appeared first on Semiconductor Engineering.
Foundation IP For The AI Era: Why Execution Saves You Millions On HPC And Edge AI SoCsDesign & IP · Semiconductor Engineering · Summary
Image: Semiconductor Engineering (opens in a new tab) How a single, integrated Foundation IP platform reduces re-spin risk and integration delays and helps lower TCO. The post Foundation IP For The AI Era: Why Execution Saves You Millions On HPC And Edge AI SoCs appeared first on Semiconductor Engineering.
Using AI for Analog DesignMarkets & Policy · Semiconductor Engineering · Summary
Image: Semiconductor Engineering (opens in a new tab) The growing role of AI in analog and mixed-signal design, where complexity is rising, schedules are tightening, and the cost of mistakes is higher than ever. The post Using AI for Analog Design appeared first on Semiconductor Engineering.
Foundations of Power Management in the Age of AIMarkets & Policy · Semiconductor Engineering · Summary
Image: Semiconductor Engineering (opens in a new tab) Make every layer of your hardware PDN-aware and reach your maximum compute density. The post Foundations of Power Management in the Age of AI appeared first on Semiconductor Engineering.
Introducing Build-A-Chip-Bench: From Workload Specification to GDSEDA & Tools · Semiconductor Engineering · Summary
Image: Semiconductor Engineering (opens in a new tab) Evaluate AI agents from workload specification through GDS layout, using open-source tools and an open-source PDK to assess their ability to complete the chip-design workflow. The post Introducing Build-A-Chip-Bench: From Workload Specification to GDS appeared first on Semiconductor Engineering.
Anduril’s BlueChip Laptop Aims to Rebuild the U.S. PC Supply ChainMarkets & Policy · Moor Insights & Strategy · Summary
Image: Moor Insights & Strategy (opens in a new tab) Anduril and Qualcomm have unveiled BlueChip, a rugged laptop built on Qualcomm’s Snapdragon X Series that Anduril designs and assembles in the U.S. The current prototype uses 90% American-made components, and Anduril’s goal is to reach 100% in the near future.
The company plans to open orders in 2027 and is targeting the usual suspects […] The post Anduril’s BlueChip Laptop Aims to Rebuild the U.S. PC Supply Chain appeared first on Moor Insights & Strategy.
Infineon to put €1.1bn into GaN fabEquipment & Materials · Electronics Weekly · Summary
Image: Electronics Weekly (opens in a new tab) Infineon intends to build the first high-volume 300mm GaN fab by investing around €1.1 billion in its llVillach site by 2034. The EU is contributing €319 million towards the cost. […] The post Infineon to put €1.1bn into GaN fab appeared first on Electronics Weekly.
Lam and Imec pursue 3-D integrationPackaging & Test · Electronics Weekly · Summary
Image: Electronics Weekly (opens in a new tab) Lam and imec are collaborating to accelerate manufacturing readiness for 3D integration technologies supporting advanced packaging and next-generation memory. By bringing together Lam’s capabilities in deposition and etch with imec’s […] The post Lam and Imec pursue 3-D integration appeared first on Electronics Weekly.
Anduril and Qualcomm hook up for ruggedised laptopMarkets & Policy · Electronics Weekly · Summary
Image: Electronics Weekly (opens in a new tab) Yesterday, Anduril and Qualcomm said they had developed a prototype of a ruggedised laptop assembled in the US with 90% of its components sourced in the US. They call it […] The post Anduril and Qualcomm hook up for ruggedised laptop appeared first on Electronics Weekly.
SK Hynix says memory shortages to persist until 2030Markets & Policy · The Register · Summary
Image: The Register (opens in a new tab) Good for its bottom line, not great news for yours, or for the PC and smartphone markets
Keeping Inference in the Radio: Design and Measurement of a Spiking Accelerator for mmWave ISAC Activity RecognitionDesign & IP · arXiv cs.AR (Hardware Architecture) · Summary
Integrated sensing and communication allows wireless networks to recognize human activity from the channel estimates that the receiver computes anyway. The inference, however, runs on the general-purpose processors of the base station, access point or handset, which are the first components a device switches off to save energy.
Always-on sensing therefore requires a classifier that is small enough to remain powered while the rest of the system sleeps. We investigate whether Spiking Neural Netwo…
SLICE-CiM: Selective Layer-wise Inference Control Engine with Confidence-Based Early Exit for SRAM based Digital Compute-in-MemoryMarkets & Policy · arXiv cs.AR (Hardware Architecture) · Summary
Digital SRAM compute-in-memory (CIM) macros enable energy-efficient CNN inference by eliminating off-chip weight transfers; however, peripheral control logic introduces three inefficiencies: bit- slice over-activation at reduced precision (L1), unnecessary accumula- tion depth (L2), and idle precision-transition stalls (L3).
To address these, we present four synthesizable peripheral blocks: a Flush-Merge Enable (FME) controller, a Confidence-Based Early-Exit (EE) module, a Precision Register wi…
Kernel Performance Engineering under Physical Non-IdealitiesDesign & IP · arXiv cs.AR (Hardware Architecture) · Summary
Physical non-idealities in integrated circuit (IC) design and fabrication are concealed by conventional hardware abstractions, yet they can limit kernel performance and obscure optimization opportunities.
Using distributed shared memory (DSMEM) on NVIDIA H100 GPUs as a case study, we show how floorsweeping restricts hardware resources available for clustered execution, potentially offsetting the benefits of reduced data movement enabled by DSMEM. Guided by these insights, we develop a wave-awar…
AnalogScout: Simulation-Efficient PVT-Aware Analog Sizing with LLM AgentsEDA & Tools · arXiv cs.AR (Hardware Architecture) · Summary
Analog device sizing must satisfy all specifications across process, voltage, and temperature (PVT) corners to ensure tape-out success, but simulating every candidate at all corners dominates the sizing time and slows design iteration.
Conventional surrogate-based optimizers search the sizing space directly, while recent large language model (LLM) agents add circuit knowledge to designs but still delegate the sizes to global optimizers. Both learn the circuit response from repeated multi-corner…
Hardware-Matched Spiking Neural Networks for Real-Time Purkinje Cell Spike ClassificationMarkets & Policy · arXiv cs.AR (Hardware Architecture) · Summary
Distinguishing Purkinje cell (PC) simple spikes (SSs) from complex spikes (CSs) is key to studying cerebellar function. PC recordings commonly rely on wired headstages, whose tethers restrict natural movement in freely behaving animals.
Untethered headstages remove this constraint, but cannot continuously transmit raw recordings within their power budgets, making on-headstage spike classification an attractive form of compression, provided it runs accurately in real time on constrained hardware…
p-DCIM: A 28nm Probabilistic SRAM DCIM based Ising Machine for Near-Memory Context Selection in LLM-RAG PipelineMarkets & Policy · arXiv cs.AR (Hardware Architecture) · Summary
We present a fabricated SRAM DCIM Ising machine that performs set-level context selection for large language model (LLM) with retrieval-augmented generation (RAG). In RAG, the evidence-selection stage is increasingly delegated to repeated language-model reranking, which adds substantial energy to the inference pipeline.
We reformulate evidence selection as a quadratic unconstrained binary optimization (QUBO) problem and solve it on a dual-mode digital compute-in-memory (DCIM) macro: the same mu…
A State Augmented Approach to Paralle Modeling in High-Level SynthesisMarkets & Policy · arXiv cs.AR (Hardware Architecture) · Summary
High-level synthesis (HLS) can schedule only the concurrency made legal by its input description. For feedback-coupled designs, a sequential behavioral model can obscure the architectural state boundaries and hazard resolution needed for efficient overlap.
We develop an explicit architectural modeling methodology based on synchronous sequential processes that start in lockstep and synchronize completion before repeating. Persistent state, communication, and feedback control are represented in C…
RV565: Cross-Layer Co-Design for Frame-Independent Video Playback on MicroPython-Class ESP32-S3 SystemsDesign & IP · arXiv cs.AR (Hardware Architecture) · Summary
Video on SPI-attached microcontroller displays is limited less by decoding than by where each byte lives and which stages run serially.
We present RV565, a decode framework for frame-independent video whose decoded representation is the panel's native RGB565 format, and evaluate it on an ESP32-S3 with two ten-second windows of an openly licensed film.
A serial path - inflate, then scale into internal-memory stripes overlapped with SPI direct-memory-access (DMA) transfers - meets the 41.7 ms dea…
Sony Semiconductor Solutions to Release Approx. 50-Effective Megapixel CMOS Image Sensor for Mobile Applications With Superb Low-Light Performance and 4K HDR Video RecordingMarkets & Policy · PR Newswire · Summary
Image: PR Newswire (opens in a new tab) Delivering top-tier technology honed in the LYTIA high-end series ATSUGI, Japan, Oct. 28, 2026 /PRNewswire/ -- Sony Semiconductor Solutions Corporation (Sony) today announced the upcoming release of the LYTIA 720, an approximately 50-effective megapixel*1 image sensor for mobile...
Amazon ECS now supports GPU sharing with NVIDIA Multi-Process Service (MPS)Design & IP · AWS pricing (EC2 / capacity blocks) · Summary
Amazon Elastic Container Service (Amazon ECS) now supports GPU sharing with NVIDIA Multi-Process Service (MPS), enabling you to run multiple Amazon ECS tasks concurrently on a single NVIDIA GPU.
GPU sharing helps you increase GPU utilization and reduce infrastructure costs for workloads that use only part of a GPU's capacity, such as small-model inference, AV/ADAS simulations, embedding generation, and multi-model serving. With GPU sharing, you can pack more workloads onto each GPU instance wit…
F5 Makes Its Case for the Layer Between AI Demand and AI Infrastructure — Analyst InsightMarkets & Policy · Moor Insights & Strategy · Summary
Image: Moor Insights & Strategy (opens in a new tab) The recent AI Infra Summit in Santa Clara, California, was, by design, a show about the bottom of the AI stack.
The organizers framed the event around a fairly straightforward position: AI has cost, energy, and scalability problems, and solving them now depends as much on how infrastructure is operated as on how much infrastructure […] The post F5 Makes Its Case for the Layer Between AI Demand and AI Infrastructure — Analyst Insight appeared first on Moor Insights & Strategy.
SK Hynix profits soar amid roaring AI chip demandMarkets & Policy · Financial Times - Semiconductors · Summary
South Korean group posts better than expected operating profit for third quarter and announces stock buybacks
Gate-level sim hung on every multiply in my RISC-V chip. The cause was X-pessimism in PicoRV32’s multiplier counterDesign & IP · r/chipdesign · Summary
Image: r/chipdesign (opens in a new tab) Some context: Argo is my PicoRV32 + 8x8 systolic array SoC on IHP SG13CMOS5L (posted here a few weeks ago https://www.reddit.com/r/chipdesign/comments/1wzfdef/i_designed_a_riscv_chip_with_a_matrix_accelerator/ ). Since then it’s been signed off for tapeout at IHP.
The RTL regression was clean. On the routed netlist, a hello-world passed, but the array test and the power-on self-test never printed anything.
They just hit the timeout. Narrowing it down I wrote a tiny test that prints a token afte…
A viable alternative to braided shielded cableMarkets & Policy · EDN (Electronics Design News) · Summary
Braided shielded cable is the standard, but a new alternative may provide superior RF performance along with other beneficial attributes. The post A viable alternative to braided shielded cable appeared first on EDN.
Part 1. The Evolution of AI and AI Chips – and the HBM That Powers ThemPackaging & Test · Samsung Semiconductor · Summary
Image: Samsung Semiconductor (opens in a new tab) As AI becomes capable of understanding long documents, answering complex questions, and performing multiple tasks, the demands on the semiconductors behind...
SK Hynix third-quarter profit sharply beats estimates on AI memory boostMarkets & Policy · CNBC Technology · Summary
Image: CNBC Technology (opens in a new tab) South Korean chipmaker SK Hynix on Wednesday reported its third-quarter earnings.
