News from October 2026

It was another interesting week for AI-related startup funding, with a number of large rounds and quirky companies. The largest financings went to Tenstorrent, a developer of AI processors and systems, and AI lab Flapping Airplanes.

The quirkiest round, meanwhile, was undoubtedly a $200 million financing for Warhound, which wants to breed elite military dogs. A number of big rounds in areas including biotech, space tech and physical AI rounded out the list.

Hi everyone! I'm currently pursuing my B.Tech in Electronics and Instrumentation Engineering, and I'm interested in building a career in the VLSI industry.

My main interests are analog IC design and physical design, although I'm also considering learning the RTL-to-GDS flow to understand the overall chip design process. I'm still a beginner when it comes to practical VLSI implementation.

I have some basic knowledge of digital electronics, Verilog, logic gates, counters, and MOSFET amplifier con…

help me decide engineer. i'm a fresh grad licensed mechanical engineer. planning to enter semicon industry. which is better? Good pay is korean company, Lower pay is a japanese company.

Same benefits tho submitted by /u/ImaginaryMango5739 [link] [comments]

Yoe: 3+ Current company: Micron Hyd Compensation offered: 20% hike with RSUs Am I getting lowballed as the HR said that they match my compensation to those from my batch i.e. 2023. This felt new to me as it's my first switch that too came out of nowhere and I prepared and cleared all rounds.

The team is STA Timing but the location they prefer(as most of the team sits) is BLR. I have little idea of the director/Sr.

Manager and manager, need help with knowing the team culture, behaviour, workload…

I have an Electronics Engineering degree and a Master's, with around 5 years of semiconductor experience working with ATEs (UltraFLEX, ETS, LTX). I moved to pure software development about 8 years ago due to limited opportunities in the local market, and have been doing that ever since.

I'm now a software dev lead. I'm looking at overseas opportunities, specifically semiconductor jobs in Germany since it seems like a good place to raise the family., preferably ATE Test or Applications Engineeri…

I’ve been selected to interview for the Engineering Intern role in Samsung Austin Semiconductor’s Production & Systems department. Could anyone explain what this role involves and what the interview process is like?

Is it more focused on semiconductor manufacturing or software engineering. There isn’t much information available online about this specific role, so any insights from current/former employees or past candidates would be really helpful.

Thanks! submitted by /u/Several-Database3286 […

submitted by /u/randomm_shitt79 [link] [comments]

Got a JG28 Senior Process Engineer offer at Texas Instruments in Dallas. Got another Senior Process Engineer offer at Tesla Solar manufacturing in Houston.

I currently live in Houston. Which of the two is better?

Background: Have a PhD with 7 years of experience in HVM semiconductor and advanced materials manufacturing. submitted by /u/One-baze [link] [comments]

I’m looking at applications role at Onto in the Boston area, on the inspection side. Anyone here worked there or know the teams?

I’m currently at another semiconductor equipment company. My background is mostly instrumentation, process development, and customer troubleshooting.

The role sounds interesting, but I’m trying to get a feel for what it’s actually like once you’re there. How are the growth opportunities?

Do people get promoted and have room to grow technically? Also curious how compet…

Hey everyone!

So recently got laid off from an MNC where i was working as a contract in the embedded field i have experience on PRE and POST silicon validation and IO peripheral validation ( UFS). searching for the new opportunity,any advices always welcome and also if you refer me then my first salary would be yours as referral gift 😅 submitted by /u/ganni1310 [link] [comments]

I'm about to join a memory semiconductor company (big 3) as a Process Engineer, and I've been told that I can express my preferences for which department I'd like to join. I have a PhD in Materials Science, and I'm trying to make a strategic decision about which department would offer the best long-term career opportunities.

Which area would be best for long-term career growth and future job mobility? I have hands on experience of ALD/ Etch/ PVD,CVD/ Litho (I've heard that photolithography, etc…

Daniel is joined by Dr. Farimah Farahmandi, co-founder and chief scientist for security verification at Caspia Technologies. Farimah is the Endowed Professor in Hardware Security and Assistant Professor at the University of Florida ECE.

She is the founding director of the Silicon Design and Assurance Laboratory there and… Read More

Azure Backup now supports Item-Level Recovery (ILR) for Azure virtual machines using Premium SSD v2 and Ultra disks with both 512 byte and 4KB logical sector sizes. You can now recover individual files and folders from your Azure VMs with Premium SSDv2 an

The U.S. is Making HBM-Free Chips. Why Isn’t China?

Most of the AI conversation stops at the chip. At SEMICON West 2026 I sat down with René Jonker, Chief Product Officer of Soitec, to talk about what sits underneath it.

Ask an engineer where AI performance comes from and you will hear about process nodes, dataflow, HBM stacks and interconnect fabrics. Rarely about the wafer.

Yet a … Read More The post The Wafer Is the New Battleground: Soitec CPO René Jonker on Building AI from the Substrate Up appeared first on SemiWiki.

Expensive EDA licenses should keep chip design moving. Yet when license activity and job queues live in separate systems, teams can struggle to understand why work is waiting, which tools are underused, and whether additional spending will solve the problem.

Idle seats, checkout failures, and stalled jobs can consume budgets… Read More The post WEBINAR: Cut down EDA License cost by 25% with Stratos AI Nitro appeared first on SemiWiki.

The future of intelligent computing depends on silicon that delivers more performance within tighter power and thermal limits.

Combining TSMC’s advanced process technology with Analog Bits’ analog and mixed-signal expertise, we help designers address those demands through local power regulation, supply monitoring, precision… Read More The post Inside the Silicon: Analog Bits N2P2 Test Chip appeared first on SemiWiki.

We take a look at the MSI XpertStation WS300, the company's top local AI solution powered by the NVIDIA DGX Station platform The post MSI XpertStation WS300 Review NVIDIA DGX Station GB300 appeared first on ServeTheHome.

The US government has taken a share in fusion energy company Helios in return for a $175 million Chips Act grant. The grant comes with an additional private investment of […] The post Washington takes stake in fusion company appeared first on Electronics Weekly.

“The AI race is often framed as a race for bigger models, faster chips and larger datacentres, – that framing is outdated,” says Patrick Vandenameele (pictured below), CEO of imec, […] The post The AI Race, by imec appeared first on Electronics Weekly.

Google and Synaptics launching an xMCU, datacentre CPU growth outpacing GPUs and ASICs, and Microsoft pulling out of Nscale's UK datacentre project... The post Most Read – xMCUs, NVHBM base dies, Qualcomm layoffs appeared first on Electronics Weekly.

CHIPS Act $389M to power chips, vertical GaN, materials; Micron's memory roadmap; Nvidia expands supply chain capacity; Tenstorrent raises $1.5B; China NAND fabs; 800V power for AI data centers; Intel advances Arizona fab; China orders +$35B in Nvidia GPUs. The post Chip Industry Week In Review appeared first on Semiconductor Engineering.

The $2 damages award grabbed headlines, but the Arm-Qualcomm verdict’s bigger implication concerns who controls the compliance tests that custom chips must pass before shipping. The post Two Dollars and a Test Suite appeared first on EE Times.

Arm's Ami Badani cites the $2 nominal damages award as validation, while chip design experts point to open architectures such as RISC-V as the long-term alternative for AI workload flexibility. The post Arm Comments on Jury Decision in Qualcomm Trial appeared first on EE Times.

Many engineers are more comfortable working behind the scenes developing technology than speaking to consumers about products.

But Preethi Ashwath has learned to take center stage, talking about the “hearable” and wearable devices she has had a hand in developing as an analog integrated circuit designer in the consumer electronics division at Analog Devices of Wilmington, Mass.

The IEEE member is one of the few women who work in the specialized field, where about 11 percent are female, accordin…

SHENZHEN, China, Oct. 23, 2026 /PRNewswire/ -- The 5th GMIF Innovation Summit (Global Memory Innovation Forum 2026, GMIF2026), co-hosted by the Shenzhen Memory Industry Association (SMIA) and the School of Integrated Circuits at Peking University, recently concluded at the Renaissance...

TUSTIN, Calif., Oct. 23, 2026 /PRNewswire/ -- Advantech (TWSE: 2395), a global leader in Edge Computing and Industrial Edge AI solutions, celebrated the grand opening of its new North American headquarters in Tustin, California this week with a two-day event that brought together local...

NVIDIA's Grace Hopper (GH200) superchip represents a new generation of heterogeneous computing, tightly integrating a 72-core Arm-based CPU with a Hopper GPU on a single module via a high-bandwidth, cache-coherent interconnect.

By eliminating the conventional PCIe bottleneck for CPU-GPU data movement, this design establishes a unified memory domain that scales to the capacities demanded by generative AI and high-performance computing (HPC) workloads. The architecture also introduces hardware-as…

Ray tracing (RT) generates photorealistic images by simulating the physical behavior of light as it interacts with surfaces in a virtual scene.

In film production and high-end rendering pipelines, this technique computes global illumination, reflections, refractions, and soft shadows by tracing millions of light rays per frame and accurately modeling their bounces and attenuation.

Contemporary GPUs incorporate specialized ray tracing hardware to accelerate key operations in the traversal pipeli…

GPUs rely on massive thread-level parallelism to tolerate long memory latency, yet they still suffer severe stalls when many warps simultaneously wait for data from the memory system.

Address-prediction-based GPU prefetchers can mitigate such stalls, but accurate prediction alone does not guarantee performance improvement: a predicted prefetch becomes beneficial only if it is worth issuing, arrives at the right time, and is retained without harmful interference. Because these requirements inter…

Modern shotgun proteomics generates tens of thousands of tandem mass spectra per hour, producing hundreds of gigabytes of data that strain conventional clustering pipelines.

DBSCAN and hierarchical agglomerative clustering (HAC) offer flexible similarity search, but DBSCAN is unstable across varying data densities, HAC costs $O(n^2)$, and both yield poor cluster quality. Graph-based methods such as Louvain produce high-quality clusters but scale poorly on streaming data.

We observe that Louvain…

Weight-only quantization keeps LLM activations in floating point and stores weights as low-bit integers, turning the dominant workload into floating-point-integer (FP-INT) general matrix multiplication.

Recent quantizers reach a 2-3-bit average with mixed precision, but hardware has not kept pace: GPUs dequantize weights to FP16 before the tensor-core multiply-accumulate, and bit-parallel FP-INT accelerators run at a single weight precision, so fewer bits save memory but not computation. In thi…

Spatial Memory Streaming (SMS) prefetchers exploit recurring spatial access patterns across memory regions to predict future accesses. Despite their effectiveness, existing SMS-based designs suffer from coarse control over aggressiveness and limited adaptability to dynamic program behavior and historical patterns.

In this work, we present Proba, a feedback-directed SMS-based prefetcher that integrates probabilistic pattern updates, marginal accuracy decision-making, and pattern accumulation ove…

We propose an end-to-end software pipeline for solving and validating DRAM address mapping functions on embedded LPDDR5 systems, and we instantiate it on embedded platforms.

Starting from a large latency dataset of address pairs, the pipeline first builds a latency histogram and then performs a threshold sweep to obtain candidate same-bank address pairs. For each threshold, we apply a Knock-Knock-style linear-constraint solver to recover candidate bank masks.

Final bank masks are calculated usi…

Elon Musk says ASML and other semiconductor equipment suppliers are expediting deliveries for Terafab, as Tesla and SpaceX target volume chip production in Texas by late 2028 alongside a massive expansion in AI compute capacity.

A bit of a shock considering their hiring spree, if the 7% figure is accurate. If this has you applying elsewhere, application autofill can save retyping your profile on supported forms.

Any word on which specific groups in HW might be targeted? submitted by /u/nian2326076 [link] [comments]

I’m planning a career in semiconductor chip design and want honest opinions from experienced industry professionals. Which is more resistant to AI automation: Analog VLSI Design or Digital Physical Design (Backend VLSI)?

I’m particularly interested in: Analog IC Design: transistor-level design, PLLs, ADC/DAC, RF and power management. Analog Layout: custom layout, matching, parasitic effects and physical verification.

Physical Design: floorplanning, placement, CTS, routing, timing closure and po…

https://preview.redd.it/89jujcmij0xh1.png?width=1262&format=png&auto=webp&s=4d12abdfe21003c6068d9874e7d0f307f055a236 I have a few questions... (1) Is this a valid schematic that works?

I was browsing on analog canvas (source: Source: https://analog-canvas.tokenzhang.com/g/rxsbettj48 )and found this circuit. Did not quite understand so I wanted to shoot my shot here.

(2) If this is a valid circuit, can someone explain to me how SIG_UVLO is sensed. Im not quite sure I understood the biasing of th…

Hi everyone, I recently connected with an internal contact regarding open hardware/systems engineering roles at a Tier-1 semiconductor equipment manufacturer.

While I am a 3rd-year Electrical & Electronics Engineering student, the team specifically hires for full-time positions rather than student/intern roles, and I confirmed immediate availability for full-time work across several hardware engineering openings.

While waiting on the next screening and technical interview rounds, I want to proa…

Staff AMS design Engineer at a startup called Lumilens that makes optical interconnects and (possibly Lead) Engineer at Cadence in the UCI Phy team that might move to Serdes in the future (their words). I have 9 years of work ex so in my mid 30s, female.

I really really wanted to get into a Serdes team and right now Cadence seems like it won't be doing a Serdes architecture. On the other hand Lumilens is just going to be zero work life balance for the next few years, but it's the work I always …

Hey guys, Ive been doing MMIC design for the last 5 years (4 as a student post and tge last year as a full time engineer). I see that Mmic is a nieche and I wanted to explore moving to RFIC/analog/mixed-signal- but from sensing my CV I saw that I didnt get much replies.

Does anyone know what can I do to branch out? Because I fear that focusing in MMIC will limit me in my future carreer submitted by /u/Ok_Jury_2715 [link] [comments]

Folks, I’ve just come to realise that we might actually be getting shortchanged when it comes to the content we learn in our schools here in Africa. With a BSc in EEE and an MSc in Telecommunication Engineering, I still find myself struggling to connect some of the theoretical knowledge we acquired in school to real-world applications.

It was only recently, when I started learning about PCB design on YouTube, that things began to make more sense. As I progressed, I found myself working with dif…

Hi This is about Quantum Odyssey, my love letter to everything Quantum Computing and the fundamental logic blocks everything in our universe seems to run on. I want to update you all on the fact that the latest patch brings the game into an almost complete status.

All that's missing is translations. Thank you Reddit community for receiving the game so well, without you I wouldn't have the funds needed to complete my life's work.

If you are remotely interested in deep diving how differently quan…

Kazakhstan’s AI ecosystem is moving from infrastructure plans to deployment. The shift is visible across the full AI stack — from infrastructure to models to applications.

Together, the ecosystem announcements below point to the nation’s increasing supply of accelerated computing — along with its growing demand for what comes next. Read All NVIDIA in Europe […]

NI said Kaynes Semicon has selected its semiconductor test systems, while other Indian OSATs continue to evaluate equipment as manufacturers prepare for production. The post India’s OSAT Buildout Puts Semiconductor Testing in Focus appeared first on EE Times.

Intel Ohio One is making progress with truss installation as part of its construction and future wafer capacity The post Intel Moves Forward at Ohio One With First Major Structural Truss Installation Arizona Fab 62 Tooling appeared first on ServeTheHome.

Deepening “symbiosis” with artificial intelligence model start-up DeepSeek is helping Chinese tech champion Huawei Technologies catch up with Nvidia’s chip hardware and software ecosystem in a scenario that could mean Jensen Huang’s “nightmare is starting to come true”, according to a new report.

DeepSeek’s latest software releases, on top of its increased experimentation with Huawei’s powerful Ascend 950PR chips, reveal that the technological gap with the US is closing, as the two firms...

GPU chief doesn't want to hear about job losses or the end of human civilization

By nearly every technical measure, today’s chips are astonishingly fast, yet phones still hesitate and cloud applications stall.

Faraj Aalaei of Cognichip argues the problem isn’t that innovation has slowed but that the industry is optimizing for the wrong definition of speed: “We didn’t run out of performance — we lost it in translation.” The post Why “Faster Chips” Don’t Feel Faster appeared first on Semiconductor Digest.

As AI moves from model development to widespread deployment, the definition of a good AI chip is changing. Inference runs continuously across millions of devices under tight limits on latency, power, cost, memory and privacy, writes Ankur Saxena of TDK Ventures, and raw compute output is no longer the main benchmark.

The post The Five Factors Defining the Next Generation of AI Inference Chips appeared first on Semiconductor Digest.