News from November 2026
673 stories of semiconductor news published on the Hub in November 2026, newest first and grouped by day (UTC). Each headline opens the story's page on the Hub, with a summary and a link to the original report.
Showing 1 to 50 of 673 stories.
Wednesday 11 November 202618 stories
TSMC to invest in Anthropic, OpenAI, raise quarterly dividendFoundry & Manufacturing · Focus Taiwan (CNA) · Summary
Image: Focus Taiwan (CNA) (opens in a new tab) Taipei, Nov. 11 (CNA) Taiwan Semiconductor Manufacturing Co. (TSMC) has approved plans to invest in artificial intelligence (AI) developers Anthropic and OpenAI and raise its quarterly cash dividend to a record NT$9 (US$0.27) per share, the company said Tuesday.
An Open Implementation Flow for the Xilinx Spartan-3E and Spartan-6 that Runs in the Browser, Checked Byte for Byte Against ISEMarkets & Policy · arXiv cs.AR (Hardware Architecture) · Summary
The author describes an open implementation flow, from HDL to a programmable bitstream, for the Xilinx Spartan-3E (XC3S100E to XC3S1200E) and Spartan-6 (XC6SLX16, XC6SLX45), devices that only the discontinued ISE 14.7 supports.
The flow runs unchanged in a web browser or in Node.js: Yosys and nextpnr compiled to WebAssembly, with nextpnr's Himbaechel framework given Spartan-3E and Spartan-6 architectures generated from Silinx's own device descriptions, bit database and timing model, and Silinx'…
SPMW: A Grid-Based Programming Model for Scalable Accelerator DesignDesign & IP · arXiv cs.AR (Hardware Architecture) · Summary
Modern accelerators specialize recurring computation and replicate it across regular hardware structures to achieve high performance. Sustaining this parallelism requires equally deliberate data delivery.
Yet design tools often express these structures as sequential programs or flatten them into separate hardware modules and connections. This obscures shared patterns and leads to repeated compiler work.
We introduce Single Program, Multiple Connected Work Units (SPMW), a grid-based programming …
SkipLane: Write-Once, Conflict-Free Accumulation for Zero-Skipping CNN Engines on FPGAsDesign & IP · arXiv cs.AR (Hardware Architecture) · Summary
Skipping zero activations saves multiplications in CNN accelerators, but it complicates accumulation: the products in a compressed input window belong to different output columns and must be merged.
In our earlier engine, this merging was done by read-modify-write (RMW) of a row buffer, which made sparse inputs slower than dense ones even at 87% sparsity. Existing designs either merge kernel rows through RMW or reduce bank conflicts with extra hardware, without eliminating them.
SkipLane makes …
SFU-Sim: Bit-Exact Reverse Engineering of NVIDIA MUFU and Validation of PTX PathsDesign & IP · arXiv cs.AR (Hardware Architecture) · Summary
Reproducing the numerical behavior of a GPU requires predicting the exact output of special function instructions. Vendor documents give only the function semantics and error bounds.
These do not fix the output bit pattern. We present SFU-Sim, which builds bit-exact models of NVIDIA multi-function unit (MUFU) instructions by black-box reverse engineering on real GPUs.
We first model a single bare MUFU instruction. We then add the surrounding operations found in the disassembly to model full PTX…
Uncovering the Memory Hierarchy of Modern NVIDIA GPUs for Accurate SimulationDesign & IP · arXiv cs.AR (Hardware Architecture) · Summary
Emerging artificial intelligence workloads, particularly Large Language Models (LLMs), place unprecedented demands on GPU memory systems. Consequently, architectural innovations increasingly target the memory system to alleviate these bottlenecks.
However, existing works still rely on outdated memory hierarchy models that fail to capture the complexities of modern hardware. This fidelity gap leads to inaccurate characterization and could misguide optimization strategies.
To bridge this gap, we …
Exploiting What NVIDIA Profilers Hide: Fast and Accurate Analytical GPU Performance ModelingDesign & IP · arXiv cs.AR (Hardware Architecture) · Summary
GPUs have become essential to many fields, including AI and scientific computing. As GPUs grow more complex, the design space of their hardware configurations becomes increasingly large, yet cycle-level simulators remain too slow to explore it.
Analytical models make this exploration much faster. However, existing GPU analytical models fall short of accurately predicting performance across hardware configurations, because they re-estimate or scale every stall of a warp on the target configurati…
Tri-Stack-PIM: A Heterogeneous Multi-Die 3D-Integrated Processing-in-Memory Architecture for Efficient LLM InferencePackaging & Test · arXiv cs.AR (Hardware Architecture) · Summary
Large language model (LLM) inference during autoregressive decoding is fundamentally memory-bandwidth-bound.
Existing three-dimensional (3D) stacked processing-in-memory (PIM) architectures alleviate the off-chip bandwidth wall, yet remain constrained by several limitations: physical layer (PHY), controllers, and direct memory access (DMA) engines compete with arithmetic units for advanced-node base-die area; hybrid-bonding keep-out zones fragment the base-die floorplan and impede physical desi…
ICLayout-Bench: Benchmarking LLM Agents for Custom Circuit Layout DesignEDA & Tools · arXiv cs.AR (Hardware Architecture) · Summary
Large language model (LLM) agents are being explored for circuit design, but their ability to produce high-quality custom layouts has not been extensively evaluated. ICLayout-Bench is a benchmark in which agents use electronic design automation (EDA) tools to construct and optimize GDSII layouts from transistor-level circuit netlists.
These layouts are evaluated using physical verification, parasitic extraction, and post-layout simulation. Layouts that pass the physical and functional checks ar…
Priority-Aware Deficit Round Robin for AXI4 Bandwidth Fairness in ASAP-7nm ProcessFoundry & Manufacturing · arXiv cs.AR (Hardware Architecture) · Summary
Modern systems-on-chip place real-time clients, processor cores and bulk data engines on the same AXI4 interconnect, where they contend for shared slaves.
AXI4 fixes the ordering rules and carries a 4-bit quality of service (QoS) field, but leaves the service policy to the implementer, and that policy determines how long each master waits and how much bandwidth it receives once a slave saturates.
We propose a QoS-aware deficit round robin (DRR) architecture that charges each grant in beats, and…
Advantech Powers High-Density Edge Infrastructure with the Intel Atom P6900 Processor-Based SOM-5994 ModuleDesign & IP · PR Newswire · Summary
Image: PR Newswire (opens in a new tab) TAIPEI, Nov. 10, 2026 /PRNewswire/ -- Advantech, a global leader in embedded computing and edge AI solutions, has announced the launch of the SOM-5994, a COM Express Basic Type 7 module powered by Intel Atom P6900 processors. Designed for compute-intensive edge networking, 5G...
ICsense Reports Record Growth as Demand Rises for Specialized Medical ASICsDesign & IP · Semiconductor Digest · Summary
Belgian semiconductor company ICsense reported a record year, with revenue rising 30% and profits increasing by more than 50%, driven in part by growing demand for custom chips used in brain-computer interfaces and implantable medical devices.
The post ICsense Reports Record Growth as Demand Rises for Specialized Medical ASICs appeared first on Semiconductor Digest.
Ye olde server consolidation has made Cisco push top-of-rack switching to 100GDesign & IP · The Register · Summary
Image: The Register (opens in a new tab) Newer server processors pack more cores into fewer boxes, creating a need for network speed
Hummink Unveils the BIRD Module at SEMICON Europa 2026Packaging & Test · Semiconductor Digest · Summary
Image: Semiconductor Digest (opens in a new tab) As advanced packaging plays an increasingly important role in the performance and miniaturization of electronic components, manufacturers face growing challenges in terms of yield, precision, and integration. The post Hummink Unveils the BIRD Module at SEMICON Europa 2026 appeared first on Semiconductor Digest.
Amazon EC2 G7 instances now available in additional regionsDesign & IP · AWS pricing (EC2 / capacity blocks) · Summary
Amazon Elastic Compute Cloud (Amazon EC2) G7 instances powered by NVIDIA RTX PRO 4500 Blackwell Server Edition GPUs are now available in Europe (London), Asia Pacific (Mumbai, Sydney) and South America (Sao Paulo) Regions. G7 instances deliver up to 4.6x AI inference performance and up to 2.1 graphics performance compared to G6 instances.
G7 instances also deliver faster performance for GPU-accelerated data analytics workloads. Customers can use G7 instances for deploying AI models for language…
Nvidia's Huang tries to project 'business as usual' in return to office after affair revelationMarkets & Policy · CNBC Technology · Summary
Image: CNBC Technology (opens in a new tab) Nvidia employees described the mood as "sad" as CEO Jensen Huang returned to the office after disclosing an affair.
Global Electronics Assembly Report: One segment will drive market to nearly double by 2030Equipment & Materials · Global Electronics Association (formerly IPC) · Summary
Image: Global Electronics Association (formerly IPC) (opens in a new tab) Global Electronics Assembly Report: One segment will drive market to nearly double by 2030 Chris Cicinelli Nov 10, 2026 Which markets drive the $4 trillion electronics assembly forecast, who builds the products and what could change it Industry Intelligence Key Summary SiC and GaN adoption is growing: Accuris recorded 1,057 new SiC parts and 141 new GaN parts in 2024.
Applications differ by voltage: GaN clusters at 650 V and below; SiC dominates higher-voltage applications. PCB requirements dif…
‘Safeguarding against system failures and cyber threats’: SK hynix builds trust in physical AI memoryMarkets & Policy · SK hynix · Summary
▪ SK hynix secures IEC 61508 SIL 3 industrial functional safety certification for LPDDR5X and ISO/SAE 21434-based Cybersecurity Management System (CSMS) certification product lifecycle process. ▪ Building on its industry-first TISAX certification early last year, the company expands its international
Tuesday 10 November 2026109 stories
The Next Level of Efficiency in Chip Manufacturing Is Taking Shape Below the CleanroomMarkets & Policy · Semiconductor Digest · Summary
With Subfab NetZero, DAS Environmental Experts introduces a holistic approach to reducing emissions and operating costs. The new ALCEA waste gas abatement system for NOx treatment expands the company’s portfolio.
The first installations are already in place at semiconductor manufacturers in Taiwan. The post The Next Level of Efficiency in Chip Manufacturing Is Taking Shape Below the Cleanroom appeared first on Semiconductor Digest.
Helion Signs Letter of Intent For $175 Million CHIPS Award to Advance U.S. High Voltage Semiconductor R&DMarkets & Policy · Semiconductor Digest · Summary
Funds will support next-generation semiconductor research and development in Everett, Washington, enabling substantial power module manufacturing capability in Washington state. The post Helion Signs Letter of Intent For $175 Million CHIPS Award to Advance U.S. High Voltage Semiconductor R&D appeared first on Semiconductor Digest.
ACM Research Enhances Single-Wafer Hot SPM System with Sulfuric Acid Recycle CapabilityFoundry & Manufacturing · Semiconductor Digest · Summary
New capability delivers a 70% sulfuric acid recycle rate while maintaining stringent particle control; System validated across more than 50 process layers at a foundry customer. The post ACM Research Enhances Single-Wafer Hot SPM System with Sulfuric Acid Recycle Capability appeared first on Semiconductor Digest.
Nordson Electronics Solutions Wins The 2026 Global Technology Award for the MARCH ExoSPHERE Plasma Treatment SystemMarkets & Policy · Semiconductor Digest · Summary
Nordson Electronics Solutions accepted the 2026 Global Technology Award in the Plasma Systems category for their new, MARCH ExoSPHERE plasma treatment system. The post Nordson Electronics Solutions Wins The 2026 Global Technology Award for the MARCH ExoSPHERE Plasma Treatment System appeared first on Semiconductor Digest.
CEA-Leti Launches SubFAB Labs with ISRL to Speed Adoption of Lower-Impact Chip Manufacturing TechnologiesPackaging & Test · Semiconductor Digest · Summary
CEA-Leti today launched SubFAB Labs, a joint program with International SubFAB Research Labs (ISRL) that gives the semiconductor industry a pre-industrial environment to test, validate and qualify technologies that reduce the environmental impact of chip manufacturing.
The post CEA-Leti Launches SubFAB Labs with ISRL to Speed Adoption of Lower-Impact Chip Manufacturing Technologies appeared first on Semiconductor Digest.
QuickLogic Reports Fiscal Third Quarter 2026 Financial ResultsDesign & IP · PR Newswire · Summary
SAN JOSE, Calif., Nov. 10, 2026 /PRNewswire/ -- QuickLogic® Corporation (NASDAQ: QUIK) ("QuickLogic" or the "Company"), a developer of embedded FPGA ("eFPGA") Hard IP, Strategic Radiation Hardened and Antifuse FPGAs, and ruggedized programmable logic solutions, today announced its...
Renesas Expands Renesas 365 with Xplore Developer HubDesign & IP · Embedded.com · Summary
Renesas Electronics Corp. has expanded its Renesas 365 development platform with the introduction of the Xplore Developer Hub, a cloud-based environment designed to simplify embedded system development and accelerate the transition from concept to prototype.
The new offering integrates low-cost RA microcontroller development boards, expansion modules, application software, and development tools into a single workflow [...] The post Renesas Expands Renesas 365 with Xplore Developer Hub appeared …
Siemens Launches HyperLynx Agentic ToolkitEDA & Tools · Embedded.com · Summary
Siemens has announced the HyperLynx Agentic Toolkit, a new solution that combines agentic AI with physics-based simulation to streamline electronic systems verification. Built on the HyperLynx platform, the toolkit automates complex verification workflows, simplifies result analysis, and supports faster engineering decisions.
As electronic systems evolve toward 112G and 224G data rates, design verification becomes increasingly [...] The post Siemens Launches HyperLynx Agentic Toolkit appeared f…
CXO Interview with Solaiman Rahim of ChipAgentsEDA & Tools · SemiWiki Forums · Summary
Dr. Solaiman Rahim is a multidisciplinary technology executive with over 25 years of experience driving innovation in the chip automation space at the intersection of systems, semiconductors, high-performance computing, and AI.
As Chief Product Officer at ChipAgents, he leads the scaling of the Agentic and Native AI platform… Read More The post CXO Interview with Solaiman Rahim of ChipAgents appeared first on SemiWiki.
CGD partners with Ricardo on developing traction inverters for Nissan-led ventureEquipment & Materials · Semiconductor Today · Summary
Fabless firm Cambridge GaN Devices Ltd (CGD) — which was spun out of the University of Cambridge in 2016 to design, develop and commercialize power transistors and ICs that use GaN-on-silicon substrates — is working with Ricardo on their development of a high-efficiency GaN-based traction inverter...
SQC Expands Executive Team With Appointment of Chief Manufacturing OfficerMarkets & Policy · PR Newswire · Summary
W.H. Teh brings 20+ years of global, multi-site operations leadership across semiconductor, photonics and AI infrastructure, including previous roles at Intel, SanDisk and NVIDIA SYDNEY, Nov. 10, 2026 /PRNewswire/ -- Silicon Quantum Computing (SQC), a pioneer in quantum computing and...
Nvidia hires law firm Wachtell Lipton to lead Jensen Huang affair probeMarkets & Policy · CNBC Technology · Summary
Image: CNBC Technology (opens in a new tab) On Sunday, Huang admitted to having an affair with a woman who has been connected to Chinese intelligence by reports in The New York Times and Financial Times.
Op-ed: In Nvidia CEO Jensen Huang's alleged China spy scandal, there's plenty of blame to go aroundMarkets & Policy · CNBC Technology · Summary
Image: CNBC Technology (opens in a new tab) In the AI era, our economic competitiveness, military capabilities, and intelligence edge can be taken down by one man. We aren't prepared.
Congress must act.
MemryX AI Unveils MX3+, Scaling AI Inference Beyond 1 POPSDesign & IP · PR Newswire · Summary
Next-generation accelerator delivers up to 10× more peak AI compute and nearly 10× more on-chip memory within the same low-power envelope as MX3 ANN ARBOR, Mich., Nov. 10, 2026 /PRNewswire/ -- MemryX AI, a fabless semiconductor company developing highly efficient and scalable AI inference...
Saskatchewan’s Semiconductor Strength Is Connecting the PiecesEquipment & Materials · EE Times · Summary
Image: EE Times (opens in a new tab) Saskatchewan brings together AI infrastructure, quantum research, chip design talent, and advanced materials expertise to expand its role in Canada’s technology ecosystem. The post Saskatchewan’s Semiconductor Strength Is Connecting the Pieces appeared first on EE Times.
Statement From the Independent Members of the NVIDIA BoardMarkets & Policy · NVIDIA · Summary
The independent members of the NVIDIA Board have retained former acting U.S. Attorney of the Southern District of New York Joon H. Kim and his firm Wachtell, Lipton, Rosen & Katz to conduct a thorough and independent investigation as was announced on Sunday.
Imec lays groundwork for open-access silicon interposer design kitPackaging & Test · Bits&Chips · Summary
Image: Bits&Chips (opens in a new tab) Imec has established the baseline manufacturing process for a silicon interposer platform on Europe’s NanoIC pilot line.
Vertical Compute and Imec take memory-on-logic design to 16 nmPackaging & Test · Bits&Chips · Summary
Image: Bits&Chips (opens in a new tab) European chip start-up Vertical Compute has expanded its partnership with Imec to validate a 40 nm test chip and prepare its first 16 nm preproduction chip.
Siemens to expand portfolio for semiconductor design and verification with the planned acquisition of LauterbachEDA & Tools · 3D InCites · Summary
Siemens has signed an agreement to acquire Lauterbach, a leading provider of debug and trace solutions for embedded software and complex system-on-chip (SoC) architectures.
Siemens has signed an agreement to acquire Lauterbach, a leading provider of debug and trace solutions for embedded software and complex system-on-chip (SoC) architectures. Lauterbach develops comprehensive, modular and extensible development […] The post Siemens to expand portfolio for semiconductor design and verification …
CPO’s Next Challenge: Turning Optical Performance into Manufacturable SystemsPackaging & Test · SemiWiki Forums · Summary
Why integration boundaries, assembly strategies, and manufacturing yield must be engineered together The Shift from Optical Performance to Manufacturing Scale Co-packaged optics (CPO) is moving beyond laboratory demonstrations toward commercial deployment in AI infrastructure.
As switch bandwidth continues to increase,… Read More The post CPO’s Next Challenge: Turning Optical Performance into Manufacturable Systems appeared first on SemiWiki.
6th Gen AMD EPYC Arrives as Agentic AI Puts the CPU Back at the CenterDesign & IP · Moor Insights & Strategy · Summary
Image: Moor Insights & Strategy (opens in a new tab) AMD’s sixth-generation EPYC processor, code-named Venice, is here, and the first systems are shipping today. The timing is notable.
AMD’s datacenter business is on an incredible run, agentic AI is reshaping the CPU market, and enterprise IT organizations face infrastructure decisions they can’t put off much longer. For CIOs, the bottom line is straightforward.
AMD’s […] The post 6th Gen AMD EPYC Arrives as Agentic AI Puts the CPU Back at the Center appeared first on Moor Insights & Strategy.
AMD's Epyc X-chips are back after a three-year hiatusEDA & Tools · The Register · Summary
Image: The Register (opens in a new tab) Venice-X promises big speedup for EDA and HPC workloads
AMD winds up Zen 6 cores for faster clock speedsMarkets & Policy · The Register · Summary
Image: The Register (opens in a new tab) Chips boast up to 256 cores, clocks up to 5.3 GHz, and IPC gains of 20-31 percent, just not all on the same SKU
AMD Zen 6 EPYC ‘Venice’ deep dive and benchmarkingDesign & IP · Tom's Hardware · Summary
Image: Tom's Hardware (opens in a new tab) AMD has pulled back the curtain on its Zen 6 microarchitecture. We deep-dive into the differences between Zen 5 and 6, as well as detail our first benchmarks of AMD’s Venice CPUs.
AMD VP and chief Zen architect rebuke claims that Nvidia and Arm made CPUs for agentic AI — ‘We didn’t magically know four years ago that agentic was going to be a thing’Design & IP · Tom's Hardware · Summary
Image: Tom's Hardware (opens in a new tab) Nvidia and Arm have new “agentic CPUs,” a title that high-ranking AMD employees are pushing back against with the launch of Zen 6 EPYC Venice CPUs.
Microsoft lobbies against potential ban on Chinese optical networking gear for AI data centers as FCC mulls restricting importsMarkets & Policy · Tom's Hardware · Summary
Image: Tom's Hardware (opens in a new tab) The ITI is lobbying against the ban of these optical transceivers needed by data centers to convert electrical signals into optical signals.
ST Unveils Unified STM32 MCU PlatformDesign & IP · Embedded.com · Summary
The unified platform adds safety-critical and mixed-signal MCUs and new and enhanced edge AI tools. The post ST Unveils Unified STM32 MCU Platform appeared first on Embedded.
AMD EPYC 9006 Results Are Here and AMD Delivers a Knockout Part DeuxDesign & IP · ServeTheHome · Summary
Image: ServeTheHome (opens in a new tab) The day is finally here for the launch of AMD's EPYC 9006 "Venice" platform and the Zen 6 CPU architecture.
AMD has been hard at work over the past two years to build a better server CPU, and thanks to its performance, Venice is primed to deliver another knockout blow for AMD The post AMD EPYC 9006 Results Are Here and AMD Delivers a Knockout Part Deux appeared first on ServeTheHome.
Netlist to Demonstrate Three CXL® Memory Proof-of-Concept Designs at the SC26 CXL PavilionMarkets & Policy · CXL Consortium · Summary
AI infrastructure, in-memory databases, and HPC workloads continue to drive requirements for memory capacity, performance, and data resilience.
At the CXL Pavilion at SC26 in Chicago, IL, Netlist will demonstrate three CXL memory proof-of-concept (POC) designs showing complementary approaches to intelligent memory tiering, data persistence, and memory expansion and reuse.
SC26 runs November 15–20, 2026; […] The post Netlist to Demonstrate Three CXL® Memory Proof-of-Concept Designs at the SC26 C…
Nick Clegg on Trump, Silicon Valley, and Big Tech’s political shiftMarkets & Policy · Atlantic Council GeoTech Center · Summary
Image: Atlantic Council GeoTech Center (opens in a new tab) Nick Clegg, former British deputy prime minister and Meta’s former president of global affairs, joins Frederick Kempe for a candid conversation about his time in government. The post Nick Clegg on Trump, Silicon Valley, and Big Tech’s political shift appeared first on Atlantic Council.
AMD Launches 6th Gen AMD EPYC Embedded Processors, Extending CPU LeadershipDesign & IP · AMD · Summary
Image: AMD (opens in a new tab) AMD EPYC Embedded 9006 Series SP7 CPUs deliver leadership performance with up to 256 cores, scalable PCIe Gen 6 and CXL 3.1 connectivity, advanced security and seven-year product longevity.
AMD Showcases 6th Gen AMD EPYC Processors to Lead Next Era of AI and Enterprise ComputingDesign & IP · AMD · Summary
Image: AMD (opens in a new tab) AMD Showcases 6th Gen AMD EPYC Processors to Lead Next Era of AI and Enterprise Computing
