Verilog

Notes

Created at Gateway Design Automation in the mid-1980s and later merged into the SystemVerilog standard, IEEE 1800.

Overview

Verilog is a hardware description language used to describe digital circuits at the behavioural, register transfer and gate levels, and to write simulation testbenches. Created in 1984 and standardised as IEEE 1364 in 1995, it has since been absorbed into SystemVerilog (IEEE 1800), which is today's active standard, though engineers still say Verilog for its design subset.

How it works

Verilog describes hardware as modules with ports, connected together to form a hierarchy. Inside a module, continuous assignments describe combinational logic, and procedural blocks triggered by clock edges describe registers. The syntax looks a little like C, but the semantics are different: statements describe circuitry that operates concurrently, and the simulator models time and events.

The same language serves two purposes. A synthesisable subset, written in a disciplined style, is turned into gates by logic synthesis tools. The rest, including delays, file input and output and procedural test code, is used only in simulation for testbenches and models.

Verilog was invented by Phil Moorby and released by Gateway Design Automation in 1984 with its Verilog-XL simulator. Cadence bought Gateway in 1990, and the language was opened up and standardised by the IEEE in 1995, with revisions in 2001 and 2005. Maintenance then moved to the IEEE 1800 working group, and SystemVerilog, which includes Verilog and adds verification and design features, became the standard; the IEEE lists 1364-2005 as superseded.

Examples

• A UART controller written as a Verilog module and reused across many products.
• A gate-level netlist produced by synthesis and written out as structural Verilog.
• A simple Verilog testbench applying directed patterns to a new block before a full UVM environment exists.
• FPGA designs written in Verilog and compiled with the vendor's tools.

Why it matters

Much of the world's digital logic, including large amounts of reusable IP, is written in Verilog or the SystemVerilog design subset, so RTL designers, verification engineers, synthesis engineers and FPGA developers all read and write it. Its long history means legacy code, tools and coding habits remain everywhere.

In the chip lifecycle Verilog RTL is written during design, simulated and verified, synthesised into gates, and the gate-level netlist itself is usually written out in Verilog form.

It matters most to: Design Verification Engineer, Gate-Level Simulation Engineer, RTL Design Engineer, RTL Synthesis Engineer

Common confusions

Not the same as SystemVerilog

SystemVerilog is the superset that now contains Verilog, adding classes, assertions, coverage and richer design constructs. Most new code is SystemVerilog even when people call it Verilog. Verilog vs SystemVerilog

Not the same as VHDL

VHDL is a separate hardware description language with different syntax and typing rules, standardised as IEEE 1076. Verilog vs VHDL

Not the same as Verilog-AMS

Verilog-AMS extends the language to analogue and mixed-signal modelling and is maintained separately by Accellera.

Related standards

• IEEE 1800 (SystemVerilog)

Sources

1. IEEE 1800-2023: IEEE Standard for SystemVerilog (opens in a new tab), IEEE Standards Association, 2026-10-22
2. IEEE 1364-2005: IEEE Standard for Verilog Hardware Description Language (superseded) (opens in a new tab), IEEE Standards Association, 2026-10-22
3. Verilog (Knowledge Center) (opens in a new tab), Semiconductor Engineering, 2026-10-22
4. IEEE 1364 (Knowledge Center) (opens in a new tab), Semiconductor Engineering, 2026-10-22
5. Verilog (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• SystemVerilog
• VHDL
• RTL
• HDL

Where it appears on the Hub

Used on 39 pages of the Hub. In each group, the pages that mention it most come first.