Chip lifecycle / FPGA lifecycle / Design Code Completion

Design Code Completion

Finishing the logic: the remaining features, the full integration of IP cores and any embedded processor subsystem, code reviews and lint, and trial builds of the whole design for fit and timing, while the first boards are built.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^D03 RTL & HLS Design

^A04 Design Code CompletionYou are here

^D05 Simulation & Verification

Product milestones

FPGA design milestones

APFArchitecture and pin-out freeze BRBoard released for build DCDesign code complete VSVerification sign-off

System architecture^AAO

0.5

FPGA logic design^DAAAO

FPGA verification^DA

0.5^A

Implementation and timing closure^AA

0.3

Board design^AA

0.5^A

Embedded software and drivers^DA

0.3

Board bring-up and debug^A

0.0

0.3

System validation and compliance^A

0.0

0.3

Configuration security^A

0.3

0.5

Production and supply^A

0.3

Product management^AO

0.3

Key0.0Planned0.3Early draft0.5Draft0.8Feature complete1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozen

Show this chart as a list

Design Code Completion

Where this stage sits

Stages

Product milestones

FPGA design milestones

Design Code Completion

Where this stage sits

Stages

Product milestones

FPGA design milestones

Disciplines

Register or sign in to read on