Chip lifecycle / Hard IP lifecycle / Silicon Validation & Reliability

Silicon Validation & Reliability

Bringing up the packaged test chips, measuring the macro across voltage, temperature and process corners, correlating the silicon with the models and views, and running the reliability stresses the macro needs, such as electrostatic discharge, latch-up and high temperature operating life.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^A06 Test Chip Tape-out

^D07 Silicon Validation & ReliabilityYou are here

^D08 Quality Checks & Release

IP product milestones

IP engineering milestones

HMSTR2Hard macro sign-off PSRPre-silicon release TCTTest chip tape-out FSTest chip silicon received SVSilicon validated on test chip RQTR3Reliability qualified HQSHard IP quality sign-off SPRSilicon-proven release

Hard IP architecture^AA

Locked

Circuit and RTL design^AO

Locked

Design verification^A

Locked

Physical implementation^D

Locked

Physical verification and sign-off^A

Locked^A

Characterisation and views^DD

1.0

Locked

Design for test and test^A

1.0

Test chip^A

Locked^A

Silicon validation^DA

0.8

1.0^D

Reliability and qualification^A

0.8^A

1.0^A

Foundry and process^A

Locked

IP quality and release^D

0.8

1.0^D

Hard IP product management^O

0.8

1.0^A

Key0.0Specified0.3Pre-alpha0.5Alpha0.8Beta1.0ReleasedLockedFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: Silicon Validation & ReliabilityAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

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Stages

Test Chip Tape-out^A
Silicon Validation & Reliability (this stage)^D
Quality Checks & Release^D

IP product milestones

IP engineering milestones

Hard macro sign-off (HMS) (technical readiness review TR2)
Pre-silicon release (PSR)
Test chip tape-out (TCT)
Test chip silicon received (FS)
Silicon validated on test chip (SV)
Reliability qualified (RQ) (technical readiness review TR3)
Hard IP quality sign-off (HQS)
Silicon-proven release (SPR)

Disciplines

Hard IP architecture^AA
- Test Chip Tape-out: maturity Locked. Specification locked with the version taped out on the test chip.
Circuit and RTL design^AO
- Test Chip Tape-out: maturity Locked. Design locked for the test chip; silicon findings and ports go into a new version.; Design locked for the test chip
- Silicon Validation & Reliability: maturity Locked. Design locked for the test chip; silicon findings and ports go into a new version.^A
- Quality Checks & Release: maturity Locked. Design locked for the test chip; silicon findings and ports go into a new version.
Design verification^A
- Test Chip Tape-out: maturity Locked. Verification results locked with the test chip version; models compared with silicon.
- Silicon Validation & Reliability: maturity Locked. Verification results locked with the test chip version; models compared with silicon.^A
Physical implementation^D
- Test Chip Tape-out: maturity Locked. Layout locked in the test chip database.; Layout released for the test chip
Physical verification and sign-off^A
- Test Chip Tape-out: maturity Locked. Test chip checks clean and the sign-off results locked with the database.^A
Characterisation and views^DD
- Test Chip Tape-out: maturity 1.0, Released. Timing and power views characterised across corners and released before silicon; correlated with silicon after it.
- Silicon Validation & Reliability: maturity 1.0, Released. Timing and power views characterised across corners and released before silicon; correlated with silicon after it.^A; Views correlated with silicon
- Quality Checks & Release: maturity Locked. Silicon-correlated views released and locked with this version.
Design for test and test^A
- Test Chip Tape-out: maturity 1.0, Released. Test chip program working on silicon and production test patterns final.
- Silicon Validation & Reliability: maturity 1.0, Released. Test chip program working on silicon and production test patterns final.
- Quality Checks & Release: maturity 1.0, Released. Test chip program working on silicon and production test patterns final.
Test chip^A
- Test Chip Tape-out: maturity Locked. Test chip database released and locked; packaged parts and boards follow.^A; Test chip database released
- Silicon Validation & Reliability: maturity Locked. Test chip database released and locked; packaged parts and boards follow.^D
Silicon validation^DA
- Test Chip Tape-out: maturity 0.8, Beta. Validation plan and lab ready for first silicon.
- Silicon Validation & Reliability: maturity 1.0, Released. Macro measured across corners on the test chip, with differences listed as errata.^D; Silicon measured across corners
- Quality Checks & Release: maturity 1.0, Released. Macro measured across corners on the test chip, with differences listed as errata.
Reliability and qualification^A
- Test Chip Tape-out: maturity 0.8, Beta. Reliability qualification plan final for the test chip.^A
- Silicon Validation & Reliability: maturity 1.0, Released. Reliability stresses passed on test chips, with failures analysed.^A; Reliability stresses passed
- Quality Checks & Release: maturity 1.0, Released. Reliability stresses passed on test chips, with failures analysed.
Foundry and process^A
- Test Chip Tape-out: maturity Locked. Masks made for the test chip and the process version fixed; later process changes are followed.; Test chip masks complete
- Silicon Validation & Reliability: maturity Locked. Masks made for the test chip and the process version fixed; later process changes are followed.
- Quality Checks & Release: maturity Locked. Masks made for the test chip and the process version fixed; later process changes are followed.
IP quality and release^D
- Test Chip Tape-out: maturity 0.8, Beta. Deliverables audit before silicon passed; silicon and reliability evidence being collected.
- Silicon Validation & Reliability: maturity 0.8, Beta. Deliverables audit before silicon passed; silicon and reliability evidence being collected.
- Quality Checks & Release: maturity 1.0, Released. Hard IP quality checklist passed with the silicon and reliability evidence.^D
Hard IP product management^O
- Test Chip Tape-out: maturity 0.8, Beta. Pre-silicon release offered to integrators who accept the silicon risk.
- Silicon Validation & Reliability: maturity 0.8, Beta. Pre-silicon release offered to integrators who accept the silicon risk.
- Quality Checks & Release: maturity 1.0, Released. Datasheet and integration guide final; silicon-proven release announced and supported.^A

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