Base Array Validation & Qualification

Stages

6. Base Layer Tape-out & Wafer Banking^A
7. Base Array Validation & Qualification (this stage)^A
8. Customer Design Intake & Feasibility^D

Product milestones

• Customer design accepted (CDA)

Base array and customer design milestones

• Base array verification sign-off (BVS)
• Design kit released (DK)
• Base layer tape-out (BTO) (technical readiness review TR2)
• Base wafers built and banked (WB)
• Base array validated (BV)
• Base array qualified (BQ) (technical readiness review TR3)
• Customer design feasibility agreed (DF)

Disciplines

• Platform and product management^O
  • Base Layer Tape-out & Wafer Banking: maturity 0.8, Feature complete. Platform offer drafted once the design kit is released on the verified base: customer designs can be assessed and quoted once the base is taped out and qualified.
  • Base Array Validation & Qualification: maturity 1.0, Complete. Platform offered to customers on a qualified base; each customer device is released for volume orders, and the roadmap, the platform's updates and its end of life are managed from here.
  • Customer Design Intake & Feasibility: maturity 1.0, Complete. Platform offered to customers on a qualified base; each customer device is released for volume orders, and the roadmap, the platform's updates and its end of life are managed from here.^A
• Base array architecture^A
  • Base Layer Tape-out & Wafer Banking: maturity Freeze, Frozen. Architecture locked in the base masks; a change from here would mean a new base array.
• Cell library and design kit^A
  • Base Layer Tape-out & Wafer Banking: maturity Freeze, Frozen. Cells locked into the base masks; the kit is released again once correlated with silicon, then changed only through reviewed updates notified to customers.
  • Base Array Validation & Qualification: maturity Freeze, Frozen. Cells locked into the base masks; the kit is released again once correlated with silicon, then changed only through reviewed updates notified to customers.^A
  • Customer Design Intake & Feasibility: maturity Freeze, Frozen. Cells locked into the base masks; the kit is released again once correlated with silicon, then changed only through reviewed updates notified to customers.
• Base array physical design^A
  • Base Layer Tape-out & Wafer Banking: maturity Freeze, Frozen. Base layers taped out and the layout locked in the masks and in every banked wafer once the base array is qualified; every customer design is built on it unchanged.
  • Base Array Validation & Qualification: maturity Freeze, Frozen. Base layers taped out and the layout locked in the masks and in every banked wafer once the base array is qualified; every customer design is built on it unchanged.
• Verification and equivalence: base array^A
  • Base Layer Tape-out & Wafer Banking: maturity Freeze, Frozen. Results locked with the tape-out database: regression and equivalence clean on it, and the signed-off environment handed to the customer designs.
• Test and DFT: base array^A
  • Base Layer Tape-out & Wafer Banking: maturity 0.8, Feature complete. Test structures and test access complete in the signed-off base and in its tape-out database.
  • Base Array Validation & Qualification: maturity 1.0, Complete. Test architecture proven on base wafers and the validation vehicles; every customer design's test is built on it.
• Base array validation and qualification^A
  • Base Layer Tape-out & Wafer Banking: maturity 0.8, Feature complete. Validation vehicle plan released with the base tape-out, and the banked wafers accepted.
  • Base Array Validation & Qualification: maturity 1.0, Complete. Base array validated across voltage and temperature and qualified for reliability; the results are the baseline customer devices are qualified against.^A
• Wafer bank, foundry and supply: base array^A
  • Base Layer Tape-out & Wafer Banking: maturity 1.0, Complete. Base wafers built to the first customisable layer, accepted and banked.
  • Base Array Validation & Qualification: maturity Freeze, Frozen. Wafer bank released for customer designs: the base process and the holding conditions are fixed for the platform.
• Quality and qualification: base array^A
  • Base Layer Tape-out & Wafer Banking: maturity 0.8, Feature complete. Base qualification plan set with the base tape-out.
  • Base Array Validation & Qualification: maturity 1.0, Complete. Base array qualified and the qualification family rules agreed, so each customer device can be qualified largely by similarity.
• Customer design engineering^D
  • Base Array Validation & Qualification: maturity 0.0, Planned. Customer engagement planned on the released design kit: which designs are assessed, by whom and when.
  • Customer Design Intake & Feasibility: maturity 0.3, Early draft. Customer design assessed against the base: array size, fixed blocks, timing and conversion scope agreed with the customer.^D
• Customer design implementation^D
  • Base Array Validation & Qualification: maturity 0.0, Planned. Customer implementation team, the reference flow on the taped-out base and the turnaround estimate per design agreed; no customer design taken in yet.
  • Customer Design Intake & Feasibility: maturity 0.3, Early draft. Trial mapping of the customer design onto the chosen array size for the feasibility check.
• Verification and equivalence: customer design^O
  • Base Array Validation & Qualification: maturity 0.0, Planned. Reuse of the signed-off base environment for customer designs planned, with the equivalence tools and the effort per design agreed; no customer design yet.
  • Customer Design Intake & Feasibility: maturity 0.3, Early draft. Environment: the signed-off base environment set up for this customer design, and the equivalence approach to its FPGA prototype agreed.
• Test and DFT: customer design^A
  • Customer Design Intake & Feasibility: maturity 0.0, Planned. Test for the customer design checked against the platform test architecture at intake, with test time and cost estimated for the quotation; no test plan yet.
• Wafer bank, foundry and supply: customer design^A
  • Customer Design Intake & Feasibility: maturity 0.0, Planned. Banked wafer availability, mask slot timing and unit cost checked for the customer design's volumes at intake, for the quotation; no wafers allocated yet.
• Quality and qualification: customer design^A
  • Customer Design Intake & Feasibility: maturity 0.0, Planned. Qualification needs of the customer design (grade, mission profile, standards) compared with the base array family at intake, with the owner agreed; no plan drafted yet.
• Customer programme management^D
  • Base Array Validation & Qualification: maturity 0.0, Planned. Intake of customer designs planned on the released design kit.
  • Customer Design Intake & Feasibility: maturity 0.3, Early draft. Customer requirements and FPGA prototype package taken in; quotation and statement of work agreed.^D