Clock gating

Notes

Often the single largest dynamic power reduction available, typically cutting clock network power by tens of percent.

Overview

Clock gating is a power-saving technique that stops the clock reaching a group of registers whenever their contents are not going to change, so the registers and the clock wiring that feeds them stop switching. Because the clock toggles every cycle whether or not data changes, stopping it where it is not needed cuts dynamic power directly. It does not reduce leakage: unlike power gating, it leaves the supply switched on.

How it works

In RTL, a register that loads only under some condition is written with an enable. Without gating, synthesis builds this as a multiplexer that feeds the register's output back to its input, so the flip-flop is still clocked every cycle. With gating, registers that share an enable are driven from one gated clock instead, removing the multiplexers and the wasted clock edges. Synopsys describes this conversion of enable flops into a clock gating structure as a normal part of logic synthesis, and designers can also instantiate gating cells by hand for whole blocks.

A plain AND gate on the clock is risky, because a change on the enable while the clock is high would chop the pulse and create a glitch. The usual answer is an integrated clock gating cell from the standard cell library, which holds the enable in a latch so the gate can only open or close between pulses; Synopsys recommends latch-based gating over simple AND or NOR gating. Libraries also include gating cells with an extra input for scan test.

Gating has costs. The cells add area and timing paths of their own, the gated clock tree has to be balanced during clock tree synthesis, and because registers may now hold different values the design must be verified again after gating is added.

Examples

• Synopsys Power Compiler, used within the Design Compiler flow, applying clock gating to reduce dynamic power.
• The scan gated clock cell in SkyWater's open SKY130 high-density library, which takes clock, gate and scan inputs.
• A register file whose storage registers receive clock edges only when a write is enabled.
• A processor core whose clock is gated off while it waits for an interrupt, with the supply left on so it resumes without restoring state.

Why it matters

RTL designers, synthesis engineers and low-power implementation engineers decide how much gating to use and where, clock tree engineers build the gated network, and verification and DFT engineers make sure the result still works and stays testable. Gating is often among the first and cheapest ways to cut switching power, in battery devices and large processors alike.

Related terms

• Logic synthesis
• UPF
• Clock tree synthesis
• Retiming
• Dynamic power
• Power gating

Where it appears on the Hub

Used on 9 pages of the Hub. In each group, the pages that mention it most come first.