Interposer & Substrate Design

Stages

3. Chiplet Design & Verification^A
4. Interposer & Substrate Design (this stage)^D
5. Multi-Die Sign-off^A

Product milestones

• Die and package supply agreed (SA)

Dies and package milestones

• Bump map freeze (BMF)
• Die design complete (DDC)
• Package design freeze (PDF)
• Multi-die sign-off (MDS) (technical readiness review TR2)
• Multi-die tape-out (MTO)

Disciplines

• Multi-die architecture^AO
  • Chiplet Design & Verification: maturity 0.8, Designed. Architecture complete: every die and the package checked against the partitioning and the budgets, with only agreed changes from here.
  • Interposer & Substrate Design: maturity 0.8, Designed. Architecture complete: every die and the package checked against the partitioning and the budgets, with only agreed changes from here.
  • Multi-Die Sign-off: maturity 1.0, Complete. System power and thermal signed off for the whole package against the budget at the multi-die sign-off.
• Die-to-die interface^AA
  • Chiplet Design & Verification: maturity 0.8, Designed. PHY and controller designed and frozen in every die, with the test and repair plan; channel checks with the interposer routing continue.
  • Interposer & Substrate Design: maturity 0.8, Designed. PHY and controller designed and frozen in every die, with the test and repair plan; channel checks with the interposer routing continue.
  • Multi-Die Sign-off: maturity 1.0, Complete. Die-to-die timing met over the final interposer or bridge at the multi-die sign-off.; Die-to-die timing met
• Chiplet die design^A
  • Chiplet Design & Verification: maturity 0.8, Designed. Every die designed, through its own sign-off and frozen; only fixes found by cross-die verification and the multi-die sign-off from here.^A
  • Interposer & Substrate Design: maturity 0.8, Designed. Every die designed, through its own sign-off and frozen; only fixes found by cross-die verification and the multi-die sign-off from here.
  • Multi-Die Sign-off: maturity 1.0, Complete. Every die signed off again on its final database with the final package models, and cross-die verification closed on it.^A
• Multi-die verification^A
  • Chiplet Design & Verification: maturity 0.8, Designed. Cross-die tests running on every frozen die design, with coverage closing.^A
  • Interposer & Substrate Design: maturity 0.8, Designed. Cross-die tests running on every frozen die design, with coverage closing.
  • Multi-Die Sign-off: maturity 1.0, Complete. Cross-die coverage closed and the system verification report agreed at the multi-die sign-off.^A; Cross-die verification signed off
• Interposer and substrate design^DO
  • Chiplet Design & Verification: maturity 0.5, Feasible. Interposer or bridge and substrate routing under way with the die floorplans, with first co-analysis results.
  • Interposer & Substrate Design: maturity 0.8, Designed. Interposer or bridge and substrate routed, analysed with the dies and frozen; only fixes from the multi-die sign-off from here.^DO
  • Multi-Die Sign-off: maturity 1.0, Complete. Assembly-level checks clean or waived across dies, interposer and substrate at the multi-die sign-off.
• Signal, power and thermal analysis^AAO
  • Chiplet Design & Verification: maturity 0.5, Feasible. Co-analysis of the dies and the package under way on the first routing.
  • Interposer & Substrate Design: maturity 0.8, Designed. Signal, power, thermal and warpage analysis on the frozen package and die views meets the targets.^AA
  • Multi-Die Sign-off: maturity 1.0, Complete. Signal, power, thermal and stress signed off on the final release set.^A
• Known-good-die test^AO
  • Chiplet Design & Verification: maturity 0.3, Outlined. Known-good-die test strategy agreed for every die from the interface test and repair plan.
  • Interposer & Substrate Design: maturity 0.5, Feasible. Sort program and probe hardware being developed on the die test patterns.
  • Multi-Die Sign-off: maturity 0.8, Designed. Sort program ready on the signed-off dies, with probe hardware and test limits set, waiting for wafers.
• Assembly process^DA
  • Chiplet Design & Verification: maturity 0.0, Started. Assembly flow, bump pitch and die thickness limits checked with the assembly supplier against the bump map, with the test vehicles needed estimated; no process plan yet.
  • Interposer & Substrate Design: maturity 0.3, Outlined. Assembly process plan outlined from the frozen interposer and substrate design, with the assembly supplier.
  • Multi-Die Sign-off: maturity 0.5, Feasible. Bumping, attach, bonding and underfill steps proven on test vehicles.
• Assembly and test suppliers^AA
  • Chiplet Design & Verification: maturity 0.3, Outlined. Suppliers shortlisted after capability reviews against the package and test needs.
  • Interposer & Substrate Design: maturity 0.5, Feasible. Supply agreements in place with every supplier, with quality and change notice terms.
  • Multi-Die Sign-off: maturity 0.5, Feasible. Supply agreements in place with every supplier, with quality and change notice terms.
• Final and system-level test^A
  • Multi-Die Sign-off: maturity 0.0, Started. Final and system-level test approach scoped with die test and the assembly supplier: tester and handler platform, load board lead times and test access through the die-to-die links; no test plan yet.
• Package qualification and reliability^AA
  • Multi-Die Sign-off: maturity 0.0, Started. Qualification needs listed from the package design, the materials and the thermal and warpage results.
• Product, cost and sourcing^AOO
  • Chiplet Design & Verification: maturity 0.5, Feasible. Cost model built from the partitioning and die choices, with make, reuse or buy options costed for each die.
  • Interposer & Substrate Design: maturity 0.8, Designed. Supply agreed with every supplier and the cost model approved; sampling and launch planned with lead customers.
  • Multi-Die Sign-off: maturity 0.8, Designed. Supply agreed with every supplier and the cost model approved; sampling and launch planned with lead customers.