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Implementing a large, power-dense die, often with high-bandwidth memory beside it in an advanced package, and closing timing, power integrity, physical checks and the package design together until they are signed off.
Where this stage sits
This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.
Key0.0Planned0.3Early draft0.5Draft0.8Feature complete1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: Physical Design & Package Sign-offAI impactDDisruption (red)AAugmentation (blue)OOpportunity (green)How AI is changing the workWhat the steps meanWhat the codes mean
Compiler, Runtime & Library Co-development: maturity 1.0, Complete. Reference workloads and accuracy baselines released for runs on emulation, then on silicon, in benchmarking and in customer qualification; the set is reviewed as models change.
Physical Design & Package Sign-off: maturity 1.0, Complete. Reference workloads and accuracy baselines released for runs on emulation, then on silicon, in benchmarking and in customer qualification; the set is reviewed as models change.
Tape-out: maturity 1.0, Complete. Reference workloads and accuracy baselines released for runs on emulation, then on silicon, in benchmarking and in customer qualification; the set is reviewed as models change.
Compiler, Runtime & Library Co-development: maturity 1.0, Complete. Model correlated with the verified design and released as the performance reference; used for cluster projections and compared with silicon.
Physical Design & Package Sign-off: maturity 1.0, Complete. Model correlated with the verified design and released as the performance reference; used for cluster projections and compared with silicon.
Tape-out: maturity 1.0, Complete. Model correlated with the verified design and released as the performance reference; used for cluster projections and compared with silicon.
Compiler, Runtime & Library Co-development: maturity 1.0, Complete. Architecture checked against the verified design and its performance correlation; changes only through change control.
Physical Design & Package Sign-off: maturity 1.0, Complete. Architecture checked against the verified design and its performance correlation; changes only through change control.
Tape-out: maturity Freeze, Frozen. Architecture locked in the taped-out design; changes wait for a new stepping or generation.; Architecture locked at tape-out
Compiler, Runtime & Library Co-development: maturity 1.0, Complete. Design code verified and released at verification sign-off; only reviewed fixes and engineering change orders go in.
Physical Design & Package Sign-off: maturity Freeze, Frozen. Design locked from physical design on: only approved engineering change orders go in before tape-out, and silicon bugs are root caused and fixed in a new stepping.
Tape-out: maturity Freeze, Frozen. Design locked from physical design on: only approved engineering change orders go in before tape-out, and silicon bugs are root caused and fixed in a new stepping.
Compiler, Runtime & Library Co-development: maturity 1.0, Complete. Results: coverage closed, numeric and performance checks agree with their references and open bugs are fixed or waived; the emulation platform runs the software stack.A; Coverage closure
Physical Design & Package Sign-off: maturity Freeze, Frozen. Results locked on the frozen design from physical design on: gate-level and change verification run to tape-out, then emulation runs the bring-up tests before silicon and reproduces silicon failures after it.
Tape-out: maturity Freeze, Frozen. Results locked on the frozen design from physical design on: gate-level and change verification run to tape-out, then emulation runs the bring-up tests before silicon and reproduces silicon failures after it.
Compiler, Runtime & Library Co-development: maturity 1.0, Complete. Released for first silicon: every target workload compiles and runs end to end on emulation with checked results; later releases add performance on silicon, the production release and maintenance releases.AA; Bring-up compiler release (milestone for one item)
Physical Design & Package Sign-off: maturity 1.0, Complete. Released for first silicon: every target workload compiles and runs end to end on emulation with checked results; later releases add performance on silicon, the production release and maintenance releases.
Compiler, Runtime & Library Co-development: maturity 0.5, Draft. Firmware, driver and runtime run the target workloads on emulation, with gaps tracked, at pre-silicon readiness.A
Physical Design & Package Sign-off: maturity 0.5, Draft. Firmware, driver and runtime run the target workloads on emulation, with gaps tracked, at pre-silicon readiness.
Tape-out: maturity 0.8, Feature complete. Bring-up firmware, driver and runtime feature complete and checked on emulation of the taped-out design; versions tagged for first silicon.
Compiler, Runtime & Library Co-development: maturity 0.5, Draft. Kernel library and framework integration run the target workloads on emulation at pre-silicon readiness, with gaps tracked.O
Physical Design & Package Sign-off: maturity 0.5, Draft. Kernel library and framework integration run the target workloads on emulation at pre-silicon readiness, with gaps tracked.
Tape-out: maturity 0.5, Draft. Kernel library and framework integration run the target workloads on emulation at pre-silicon readiness, with gaps tracked.
Physical Design & Package Sign-off: maturity 1.0, Complete. Timing, power integrity, physical checks and package signed off at physical sign-off, with the package models released to the board teams.
Tape-out: maturity Freeze, Frozen. Tape-out database and package design released and locked at tape-out; package models and timing data support the boards and bring-up.A; Tape-out database released
Physical Design & Package Sign-off: maturity 0.8, Feature complete. Board, power delivery and cooling designs feature complete with the package thermal and electrical models from physical sign-off.
Tape-out: maturity 0.8, Feature complete. Board, power delivery and cooling designs feature complete with the package thermal and electrical models from physical sign-off.
Compiler, Runtime & Library Co-development: maturity 0.5, Draft. Collective communication plan drafted with the software teams; chip-to-chip links checked on emulation.
Physical Design & Package Sign-off: maturity 0.5, Draft. Collective communication plan drafted with the software teams; chip-to-chip links checked on emulation.
Tape-out: maturity 0.8, Feature complete. Link budget closed with the package design at tape-out; rack power and cooling checked with the board design.
Compiler, Runtime & Library Co-development: maturity 0.0, Planned. Silicon validation approach planned with verification: what first silicon must show and how it is checked.
Physical Design & Package Sign-off: maturity 0.0, Planned. Silicon validation approach planned with verification: what first silicon must show and how it is checked.
Tape-out: maturity 0.3, Early draft. Bring-up test content written from the verification tests and run on emulation of the taped-out design.
Physical Design & Package Sign-off: maturity 0.3, Early draft. Benchmark plan final from the pre-silicon run results; the harness started on emulation.
Tape-out: maturity 0.3, Early draft. Benchmark plan final from the pre-silicon run results; the harness started on emulation.
Compiler, Runtime & Library Co-development: maturity 0.0, Planned. Test strategy and design-for-test architecture set at the RTL freeze for the die, the memory stacks and the package.
Physical Design & Package Sign-off: maturity 0.3, Early draft. Scan and memory test patterns generated on the signed-off design at physical sign-off, and the test plan final at tape-out.
Tape-out: maturity 0.3, Early draft. Scan and memory test patterns generated on the signed-off design at physical sign-off, and the test plan final at tape-out.
Compiler, Runtime & Library Co-development: maturity 0.5, Draft. Lead customers' models compiled and run on emulation with the pre-silicon software stack, and porting gaps fed back.
Physical Design & Package Sign-off: maturity 0.5, Draft. Lead customers' models compiled and run on emulation with the pre-silicon software stack, and porting gaps fed back.
Tape-out: maturity 0.5, Draft. Lead customers' models compiled and run on emulation with the pre-silicon software stack, and porting gaps fed back.
Physical Design & Package Sign-off: maturity 0.5, Draft. System offerings, pricing approach and supply plans prepared while the chip is made.
Tape-out: maturity 0.5, Draft. System offerings, pricing approach and supply plans prepared while the chip is made.
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Tape-out: maturity 1.0, Complete. Released for first silicon: every target workload compiles and runs end to end on emulation with checked results; later releases add performance on silicon, the production release and maintenance releases.