One reusable block delivered as synthesisable design code (soft IP), made in-house or taken in from a supplier, from its specification through design, verification, implementation views and quality checks to a versioned release for SoC teams.
Start here: what it is, how the related terms differ, what this lifecycle covers and its phases in order, then the detail.
Semiconductor intellectual property, usually called IP, is a reusable design for one function that is built into chips rather than sold as a chip. Examples include processor cores, memory controllers, interface controllers and their physical layers, data converters, security blocks and on-chip memories.
An IP block is delivered as a set of files: design source or layout, models, constraints, test patterns, documentation and verification material. An SoC team, in the same company or at a licensee, integrates it with other blocks into a chip.
IP comes in two broad forms. Soft IP is delivered as synthesisable design code, so the integrator builds it into the chip's own layout and can often configure it. Hard IP is delivered as finished layout for one process, which is common for analogue and high-speed blocks whose behaviour depends on the exact layout.
The IP product is the block plus what makes it usable and trustworthy: deliverables, documentation, verification evidence, quality checks, licence terms, support and a plan for later versions.
IP is a design that ends up inside someone else's chip. The terms around it:
| Term | What it is | How it differs |
|---|---|---|
| Soft IP | Synthesisable design code, often configurable. | Not tied to one process; the integrator implements it. |
| Hard IP | Finished layout for one process.For example: A high-speed interface physical layer. | Fixed size and performance, but moving to another process means new layout work. |
| Foundation IP | Standard cells, memories and input and output cells for a process. | Used by almost every design on that process, rather than adding one feature. |
| Verification IP | Models and checkers that test a design's use of a protocol. | Never part of the chip; it lives in the test environment. |
| Subsystem | Several blocks integrated, verified and delivered as one. | Saves integration work, but fixes more design choices. |
| IP release | A versioned, complete set of deliverables for stated configurations and processes. | What is actually handed over and tracked by integrators. |
| Test chip | A chip made to prove blocks in silicon. | Not a product; its results support silicon-proven claims. |
| Chiplet | A manufactured die combined with other dies in one package. | Reused as physical silicon in the package, not as a design inside the die. |
| SoC | The chip that integrates the IP. | The IP lifecycle's customer. It ends in silicon; the IP lifecycle ends in a release. |
| Licence | The agreement on who may use the IP, for what, and on what payment terms. | Governs use; the lifecycle governs what is delivered and its quality. |
The Soft IP lifecycle is the path of one block, delivered as design code, from its specification to a versioned release that SoC teams can integrate, and the maintenance releases that follow. It applies to blocks built in-house and to bought-in IP, where the work becomes evaluation, intake and quality checks rather than design.
It differs from the SoC lifecycle in what it delivers. The SoC lifecycle ends in silicon; the IP lifecycle ends in a release package, judged by how easily and safely others can use it. Its verification must cover every configuration a customer might choose, not only the one a single chip uses.
An IP product manager or IP programme manager usually owns it, with a development lead for the technical work. It runs on two tracks: business milestones such as early access and release, and engineering milestones such as freezes and sign-offs.
Gates exist because a defect in an IP block is copied into every chip that uses it, and a late fix costs each integrator more than it costs the IP team. The freezes, the verification sign-off and the quality sign-off before release are where that risk is checked.
A dotted underline opens the full definition in the glossary.
Credible sources, named for further reading. Standards are available from the body that publishes them.
Soft IP lifecycle: 8 stages, 9 gates of its own and 1 hand-off to the Product lifecycle, from IP Specification & Architecture to IP Release & Hand-off.
8 stages, 9 gates of its own and 1 hand-off to the Product lifecycle, 2 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
In collaboration with The Digital Electronics Blog (opens in a new tab)
A dashed sign with a TR tag is a technical readiness review gate.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Defining what the block must do, its interfaces and configuration options, and deciding whether to build it in-house or take it from a supplier.
IP plan approved gate, owned by the Product lifecycle (Plan approval and development commit)TR1: Technology feasibility gateTR1, technical readiness reviewIP specification freeze gate
Working out how the block is built: its internal structure, data paths, clocking and reset, configuration logic and register map, with the verification plan and the performance tracking set up alongside, until the micro-architecture is reviewed.
Writing the block's synthesisable design code until the main features are in and an early drop can go to SoC teams for integration trials and floorplanning, with its limits stated.
Completing the design code, including every configuration option and the logic an integrator connects to, with lint and clock domain crossing checks clean, until the RTL is frozen.
Closing verification of the frozen block in every supported configuration, through simulation, formal methods and coverage, with every open bug fixed or waived.
IP verification sign-off gateTR2, technical readiness review
Adding the block's test structures and producing what an integrator needs to implement it: timing constraints, a reference synthesis on a target process, timing models and test patterns.
Checking the complete set of deliverables, whether built in-house or received from a supplier, against a quality checklist before release.
Packaging a versioned release with its documentation, handing it to the SoC teams that integrate it, and supporting them afterwards.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.