Term · Design & Architecture
Hard IP
IP delivered as a fixed physical layout for one specific process, such as a PHY, PLL or memory compiler instance. Its timing, power and area are characterised and guaranteed but it cannot be retargeted.
- Also known as
- Hard macro, Hardened IP
- Type
- Term
- Domain
- Design & Architecture, IP and reuse
Notes
Analogue and high-speed interface content is almost always hard IP because its behaviour depends on device-level process detail.
Overview
Hard IP is a reusable block of chip design delivered as a finished physical layout for one specific process, so it goes into the floorplan as a fixed macro rather than being synthesised. Analogue and mixed-signal blocks, such as PHYs, SerDes, PLLs and data converters, are usually delivered this way, along with memory instances and I/O cells. Because the layout is fixed, its timing, power and area can be characterised and proven in silicon in advance, but moving it to another node or foundry means redesigning it.
How it works
A hard IP provider designs and lays out the block for one foundry process and supplies it as a layout database, typically in GDSII form, together with simplified views and timing models that let the chip's own tools place the block, connect to its pins and time the paths around it. Providers commonly prove the block in test silicon on that process before release.
Not all hard IP is a single fixed layout. A memory compiler generates hard SRAM instances of the size and aspect ratio the designer requests, within the rules of one process. Interface IP is often split: the analogue PHY is delivered hard while the digital controller is delivered as RTL. Synopsys, for example, describes its DDR multiPHYs as compiled into a hard macro optimised for specific foundry nodes, connected to RTL controller logic.
The integrator treats the block as a black box with fixed pins, shape and keep-out areas, and must follow its placement, power supply and routing requirements. Because the layout follows one foundry's design rules, hard IP ties a design to that process, and a missing or late hard block for a new node can hold up a whole chip programme.
Examples
- A DDR or LPDDR memory interface PHY delivered as a hardened macro tuned for a specific foundry node.
- SRAM instances generated by a memory compiler for the target process and placed as fixed blocks.
- A SerDes, PLL or ADC macro placed in the floorplan as a fixed block with its own power supplies.
- Foundation IP offered as part of a foundry's design infrastructure, such as the standard cell libraries, I/O libraries and memory compilers TSMC listed for its 28 nm process in 2011.
Why it matters
Hard IP supplies much of a chip's analogue and interface content, and whether the right blocks exist on a given node often decides which node a product can use. Hard IP designers, foundation IP and memory compiler engineers, floorplanning engineers and IP integration teams work with it most closely.
In the chip lifecycle, hard IP is chosen at architecture, placed early in floorplanning, checked at its boundaries during physical verification and signoff, and confirmed in silicon at bring-up. Each new node needs a new version of every hard block.
It matters most to: Floorplanning Engineer, Hard IP Design Engineer, IP Integration & Hardening Engineer, Memory Compiler & Foundation IP Engineer, SerDes Analog / PHY Design Engineer
Common confusions
- Not the same as soft IP
- Soft IP is delivered as RTL that the integrator synthesises for any suitable process, so it is portable but its final timing and power are not guaranteed. Hard IP is fixed layout for one process with known characteristics. Hard IP vs soft IP
- Not the same as any hard macro in a floorplan
- A chip team can harden its own RTL block into a fixed macro to reuse it within a design. Hard IP usually means a reused or licensed block delivered already laid out.
- Not the same as a chiplet
- A chiplet is a separately manufactured die joined to others in a package. Hard IP is layout that becomes part of the same die as the rest of the chip.
Sources
- DDR multiPHY IP (opens in a new tab), Synopsys, 2026-10-22
- Semiconductor IP, Silicon IP (opens in a new tab), Synopsys, 2026-10-22
- TSMC Completes 28nm Design Infrastructure, Design Partners Show Solutions at DAC (press release, 26 May 2011) (opens in a new tab), TSMC, 2026-10-22
- Semiconductor intellectual property core (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
Related terms
Part of the Design & Architecture glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 29 pages of the Hub. In each group, the pages that mention it most come first.
Lifecycle stages and gates
- Hard IP Selection & Integration (FPGA chip lifecycle)
- Hard IP integration plan agreed (FPGA chip lifecycle)
- Quality Checks & Release (Hard IP lifecycle)
- Specification & Process Selection (Hard IP lifecycle)
- First designs running on silicon (FPGA chip lifecycle)
- Hard IP plan approved (Hard IP lifecycle)
- and 11 more
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Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary