Foundation IP

Overview

Foundation IP is the set of basic, pre-designed and pre-verified libraries from which digital chips on a given process are built: standard cell logic libraries, embedded memories and the compilers that generate them, and input and output (I/O) cells, often joined by items such as one-time programmable memory. Nearly every design on that process uses it, so its density, speed, leakage and quality set a floor under every chip built with it. It is supplied by foundries, by IP vendors such as Synopsys, or by in-house library teams.

How it works

Logic libraries offer each cell function in several drive strengths, threshold voltages and sometimes channel lengths, so that tools can trade speed against leakage path by path. Vendors add kits for particular jobs: power optimisation kits with cells for shutting down blocks and crossing voltage domains, ECO kits that allow metal-only fixes after silicon, and high-performance kits with datapath cells and multi-bit flip-flops. Memory compilers generate SRAM instances of the size and shape a design asks for, in architectures tuned for speed or density, and I/O libraries supply general-purpose and interface-specific pad cells.

Each item comes with its layout and with models for design tools, including Liberty timing and power models produced by characterisation across process, voltage and temperature corners. Foundries run quality programmes for this IP. TSMC's TSMC9000 programme, for example, sets baseline quality criteria for libraries and IP on TSMC processes, with reviews before test-chip tapeout and silicon assessments afterwards, and customers can see the resulting scores on TSMC-Online.

Standard libraries cover common needs, but demanding targets can call for customisation. Synopsys has described redesigning a memory compiler so that memories work at 0.4 V, where ordinary bit cells are typically unreliable, and building automotive libraries with extra PVT corners and ultra-low-leakage memories for long life at high temperature. Such custom IP is usually proven on a silicon test chip before production use.

Examples

• SkyWater's seven foundry-provided standard cell libraries for its open 130 nm process, ranging from high density to a 5 V high-voltage library.
• An ECO kit of spare, metal-configurable cells used to fix a logic bug after first silicon by changing only metal layers.
• A customer checking TSMC9000 scores on TSMC-Online before choosing a library or IP block for a TSMC process.

Why it matters

Foundation IP engineers, standard cell and I/O library designers, memory compiler engineers and characterisation engineers create and maintain it, while chip teams choose which library variants and memory architectures to use early in a project. Because every design on the process depends on it, a weak cell, a poorly characterised corner or a memory bug spreads to every chip that uses it.

In the chip lifecycle, foundation IP is developed alongside a new process and its PDK, validated on test chips, selected during architecture and implementation planning, used through synthesis, place and route and signoff, re-characterised as device models mature, and supported for as long as the process runs.

It matters most to: Foundation IP Engineer, IO Library Design Engineer, Library Characterization Engineer, Memory Compiler & Foundation IP Engineer, Standard Cell Library Design Engineer

Common confusions

Not the same as interface IP

Interface IP such as PCI Express, USB or DDR controllers and PHYs implements a specific protocol. Foundation IP is the general building material used underneath every block.

Not the same as PDK

The foundry's PDK supplies design rules, device models and technology files. Foundation IP is built with the PDK and sits one level above it.

Not the same as standard cell library

A standard cell library is one part of foundation IP; memories and I/O cells are the others.

Sources

1. Foundation IP: Logic Library, Memory Compiler, OTP, NVM (opens in a new tab), Synopsys, 2026-10-22
2. Logic Library IP (opens in a new tab), Synopsys, 2026-10-22
3. IP Alliance (opens in a new tab), TSMC, 2026-10-22
4. Customizing Foundation IP For Ultra-Low-Voltage Designs (Daryl Seitzer, Andrew Appleby and Mohammad Tanveer, 12 March 2026) (opens in a new tab), Semiconductor Engineering, 2026-10-22
5. Delivering Automotive-Grade Quality With Customized FinFET Foundation IP (Andrew Appleby, Daryl Seitzer and Nafiz Ahmed, 4 June 2026) (opens in a new tab), Semiconductor Engineering, 2026-10-22
6. SkyWater Foundry Provided Standard Cell Libraries (SKY130 PDK documentation) (opens in a new tab), SkyWater Technology, 2026-10-22

Related terms

• Standard cell library
• IO ring
• PDK
• Liberty

Where it appears on the Hub

Used on 18 pages of the Hub. In each group, the pages that mention it most come first.