Chiplet

Notes

Popularised commercially by AMD's Zen processors, which paired compute chiplets on an advanced node with an I/O die on an older one.

Overview

A chiplet is a die designed to work only as part of a multi-die package, implementing one part of a system such as processor cores, I/O or memory control, and connected to other chiplets through dense die-to-die links. Splitting a large chip into chiplets improves yield, lets each function use the process best suited to it, and allows the same chiplets to be reused across products.

How it works

Very large dies yield poorly, because one defect can scrap the whole die, and the largest die a scanner can expose is limited by its field size. Breaking the design into several smaller chiplets means more good dies per wafer and makes larger total systems possible. Functions that do not benefit from the newest process, such as I/O and analogue circuits, can be built on an older, cheaper node while compute chiplets use the leading edge.

Chiplets talk through die-to-die interfaces that are short, wide and power efficient. They connect through an organic substrate for lower density, or through silicon interposers, embedded bridges or 3D stacking with hybrid bonding for higher density. Standards such as UCIe, the Universal Chiplet Interconnect Express, define the physical layer and protocols so that chiplets from different designers and foundries can work together, which would allow a market in reusable chiplets.

Chiplets bring new problems. Each must be tested thoroughly before assembly, as a known good die, because a faulty one wastes the whole package; heat, power delivery and mechanical stress must be managed across dies; and design tools, IEEE 1838 test access and security across dies all need to work at package level.

Examples

• A server processor with several compute chiplets and a central I/O die in one package.
• An AI accelerator combining compute chiplets with stacks of high bandwidth memory.
• Reusing the same I/O die across desktop and server products.
• A UCIe link joining two dies from different foundries in one package.
• Known good die testing of each chiplet before it is committed to an expensive package.

Why it matters

Chiplets have become the standard approach for the largest processors and AI accelerators, so chiplet and package architects, die-to-die interface designers, test engineers and EDA teams are in demand. They also change business models, as companies combine their own chiplets with others bought in.

In the chip lifecycle, chiplet partitioning is decided at architecture, each chiplet and the package are co-designed and verified together, known good die testing precedes assembly, and the assembled package is qualified as one product.

It matters most to: Chiplet & Die Disaggregation Architect, Chiplet Integration Architect, Chiplet System Architect, Die-to-Die Interface IP Design Engineer, Known-Good-Die & Chiplet Test Engineer

Common confusions

Not the same as SoC

A monolithic SoC integrates the whole system on one die. A chiplet design spreads it across several dies in one package.

Not the same as multi-chip module

Multi-chip modules have combined separate chips in one package for decades. Chiplets are designed from the start as parts of one system, with dense die-to-die links.

Not the same as IP block

An IP block is a piece of design integrated into a die. A chiplet is a manufactured die, which may contain many IP blocks.

Related standards

• UCIe (Universal Chiplet Interconnect Express) specification, UCIe Consortium
• IEEE 1838 (test access architecture for three-dimensional stacked integrated circuits)

Sources

1. Specifications (opens in a new tab), UCIe Consortium, 2026-10-22
2. What are Chiplets? (opens in a new tab), Synopsys, 2026-10-22
3. IEEE 1838-2019: IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits (opens in a new tab), IEEE Standards Association, 2026-10-22
4. Chiplet (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• UCIe
• KGD
• 2.5D integration
• Base die
• Die-to-die interface
• Disaggregation

Where it appears on the Hub

Used on 57 pages of the Hub. In each group, the pages that mention it most come first.