Integration guide

Overview

An integration guide is the document an IP provider supplies to tell a chip team how to put an IP block into their design: how to connect and configure it, what clocks, resets and power it needs, how to constrain and implement it, and how to verify and test it in place. It sits alongside the other IP deliverables, such as RTL or a hard macro, models, timing views and example testbenches, and it carries a revision history that tracks the IP's releases. Integration guides for licensed IP are often confidential and shared only under a non-disclosure agreement.

How it works

There is no fixed template, but two public examples show the usual ground. Achronix's Speedcore ASIC Integration User Guide (UG064, version 3.0, March 2024), for its embedded FPGA IP, first sets out who does what: tasks for the architect, the ASIC integrator and the end users. It then covers front-end integration and simulation, with pin naming that separates functional, auxiliary and DFT interfaces, the simulation deliverables and an example testbench to adapt. Further chapters cover static timing analysis, including timing modes, clocking scenarios, corners and margins and how to generate boundary constraints, and physical integration, including floorplan placement, power and ground alignment, the routing grid and IR drop analysis.

The open-source Ibex RISC-V core shows the same pattern for soft IP. Its integration page gives an instantiation template, a table of every parameter and its effect, a table of every port, the clock and active-low asynchronous reset, test-mode and scan-reset inputs for DFT, the register file options for FPGA and ASIC targets, and synthesis constraints for primitive cells that must not be optimised away.

Machine-readable files often accompany the document. IP-XACT descriptions, standardised as IEEE 1685, carry an IP block's interfaces, registers and file sets so that integration tools can use them directly, but the guide still explains the choices and pitfalls that metadata cannot.

Examples

• Achronix's Speedcore ASIC Integration User Guide, whose full contents are available only under a non-disclosure agreement.
• The Ibex core integration page, which lists every parameter and port of the core's top-level module.
• A guide's timing chapter explaining how to generate the boundary timing constraints for the IP's interfaces.
• A note that a block's scan reset input may be tied off when the design does not use DFT.

Why it matters

The guide is where requirements such as reset handling, timing constraints and test inputs are written down, so a missed or misread section leads directly to integration bugs. SoC and chip-level integration engineers rely on it, IP applications engineers support customers through it, and IP documentation engineers write and maintain it with each release.

In the chip lifecycle, the guide is read during IP evaluation and selection, used throughout integration, implementation, DFT and signoff, and revised with each IP release and erratum.

It matters most to: Chip-Level Integration Engineer, IP Applications Engineer, IP Documentation & Deliverables Engineer, IP Integration & Hardening Engineer, RTL Integration and Chip Assembly Engineer

Common confusions

Not the same as datasheet

A datasheet or databook describes what the IP does and its specifications. The integration guide explains how to build it into a chip.

Not the same as programming guide

A programming guide tells software engineers how to drive the IP through its registers. The integration guide is for the hardware team connecting and implementing it.

Related standards

• IEEE 1685 (IP-XACT, metadata for packaging and integrating IP)

Sources

1. Speedcore ASIC Integration User Guide (UG064), version 3.0, 15 March 2024 (opens in a new tab), Achronix Semiconductor, 2026-10-22
2. Core Integration (Ibex documentation) (opens in a new tab), lowRISC, 2026-10-22
3. IEEE 1685-2022: IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows (opens in a new tab), IEEE Standards Association, 2026-10-22

Related terms

• IP deliverables
• IP core

Where it appears on the Hub

Used on 8 pages of the Hub. In each group, the pages that mention it most come first.