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Deciding how to split the system into dies, which process node each die uses, and which packaging technology joins them, such as a silicon interposer, an embedded bridge, fan-out or 3D stacking.
Where this stage sits
This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.
Key0.0Started0.3Outlined0.5Feasible0.8Designed1.0CompleteFreezeFrozenFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: System Partitioning & Package ArchitectureAI impactDDisruption (red)AAugmentation (blue)OOpportunity (green)How AI is changing the workWhat the steps meanWhat the codes mean
Die-to-Die Interface Design: maturity 0.5, Feasible. Die-to-die budgets and the package power and thermal budget set against the agreed interface and bump map.
Chiplet Design & Verification: maturity 0.8, Designed. Architecture complete: every die and the package checked against the partitioning and the budgets, with only agreed changes from here.
System Partitioning & Package Architecture: maturity 0.3, Outlined. Die-to-die standard, protocol and lane count chosen with the partitioning; a first interface specification drafted.
Die-to-Die Interface Design: maturity 0.5, Feasible. Interface specification and bump map baselined with every die team, the package team and the assembly supplier.AA; Bump map baselined (milestone for one item)
Chiplet Design & Verification: maturity 0.8, Designed. PHY and controller designed and frozen in every die, with the test and repair plan; channel checks with the interposer routing continue.
Die-to-Die Interface Design: maturity 0.5, Feasible. Each die's floorplan and die-to-die placement planned against the bump map; design under way.
Chiplet Design & Verification: maturity 0.8, Designed. Every die designed, through its own sign-off and frozen; only fixes found by cross-die verification and the multi-die sign-off from here.A
System Partitioning & Package Architecture: maturity 0.3, Outlined. Cross-die verification strategy outlined with the partitioning: the die-to-die paths and system scenarios to check, and the simulation and emulation platforms.
Die-to-Die Interface Design: maturity 0.5, Feasible. Verification plan and environment built against the interface specification: die-to-die verification IP, protocol checkers and the coverage model.
Chiplet Design & Verification: maturity 0.8, Designed. Cross-die tests running on every frozen die design, with coverage closing.A
Die-to-Die Interface Design: maturity 0.3, Outlined. Substrate layer stack and bump plan set against the bump map.
Chiplet Design & Verification: maturity 0.5, Feasible. Interposer or bridge and substrate routing under way with the die floorplans, with first co-analysis results.
Chiplet Design & Verification: maturity 0.0, Started. Assembly flow, bump pitch and die thickness limits checked with the assembly supplier against the bump map, with the test vehicles needed estimated; no process plan yet.
Die-to-Die Interface Design: maturity 0.3, Outlined. Business case, product requirements and cost target approved at concept.
Chiplet Design & Verification: maturity 0.5, Feasible. Cost model built from the partitioning and die choices, with make, reuse or buy options costed for each die.
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