Base Array Architecture

Stages

1. Platform Definition^O
2. Base Array Architecture (this stage)^A
3. Base Array Design^A

Product milestones

• Concept approval (CA)
• Platform plan agreed (PP)

Base array and customer design milestones

• Platform requirements baselined (PRB)
• TR1: Technology feasibility (TF) (technical readiness review TR1)
• Base array architecture freeze (BAF)
• Base array integration complete (BIC)

Disciplines

• Platform and product management^O
  • Platform Definition: maturity 0.3, Early draft. Business case approved and the platform requirements baselined: the designs the platform is for, its array sizes, fixed blocks and turnaround; the platform plan, pricing and engineering charge model are then agreed on the frozen architecture, which commits development.
  • Base Array Architecture: maturity 0.3, Early draft. Business case approved and the platform requirements baselined: the designs the platform is for, its array sizes, fixed blocks and turnaround; the platform plan, pricing and engineering charge model are then agreed on the frozen architecture, which commits development.^A
  • Base Array Design: maturity 0.5, Draft. Platform plan managed against the base array as it is integrated and frozen, with the pricing and the engineering charge model checked against the design.
• Base array architecture^A
  • Platform Definition: maturity 0.0, Planned. Options for the configurable cell, the split between fixed and custom layers and the array sizes listed and studied against the platform requirements, ahead of any choice.
  • Base Array Architecture: maturity 0.3, Early draft. Architecture written and frozen as the input to the base design after trial mapping of the reference designs, with technology feasibility shown at the technical readiness review; its detail is filled in as the base is designed.^A; Custom layer split freeze (milestone for one item)
  • Base Array Design: maturity 0.5, Draft. Architecture confirmed against the integrated base array: the fixed blocks, cells and networks match the frozen split between fixed and custom layers.
• Cell library and design kit^A
  • Platform Definition: maturity 0.0, Planned. Configurable cell concept and the design kit plan scoped with the platform requirements.
  • Base Array Architecture: maturity 0.3, Early draft. Cell architecture chosen with the base array architecture: how the custom layers turn the cell into logic and registers.
  • Base Array Design: maturity 0.5, Draft. Configurable cells drafted and laid out in the array tile, with first timing models for the trial of the reference flow.
• Base array physical design^A
  • Platform Definition: maturity 0.0, Planned. Die sizes, the array tile and the placement of the fixed blocks listed as options for the platform.
  • Base Array Architecture: maturity 0.3, Early draft. Array tile, fixed routing and the clock and power networks trial laid out with the frozen architecture.
  • Base Array Design: maturity 0.5, Draft. Fixed blocks, cells and the clock and power networks integrated in one base array database, with the reference designs through a first trial of the flow.^A
• Verification and equivalence: base array^A
  • Platform Definition: maturity 0.0, Planned. Environment: verification strategy for the base array, its cells and fixed blocks scoped with the platform requirements.
  • Base Array Architecture: maturity 0.3, Early draft. Environment: plan, testbench and checkers started from the frozen architecture.
  • Base Array Design: maturity 0.5, Draft. Environment: plan agreed, and the testbench, checkers and coverage model running on the integrated base array.^A
• Test and DFT: base array^A
  • Base Array Architecture: maturity 0.0, Planned. Test approach for the base array scoped with the architecture: scan, built-in self-test and test access in the fixed layers.
  • Base Array Design: maturity 0.3, Early draft. Test approach outlined on the integrated base: where the test structures sit in the array and in the fixed blocks.
• Base array validation and qualification^A
  • Base Array Architecture: maturity 0.0, Planned. Validation approach scoped with the architecture: what the base must show on silicon.
  • Base Array Design: maturity 0.3, Early draft. Validation approach and the test designs that will exercise the base agreed on the integrated base.
• Wafer bank, foundry and supply: base array^A
  • Platform Definition: maturity 0.0, Planned. Process and foundry options listed against the platform's cost and turnaround targets.
  • Base Array Architecture: maturity 0.3, Early draft. Wafer banking shown feasible with the foundry, including how long wafers can be held, at the technical readiness review.
  • Base Array Design: maturity 0.5, Draft. Foundry terms and rule decks for the base design agreed, with the bank size and the wafer start plan drafted.
• Quality and qualification: base array^A
  • Base Array Architecture: maturity 0.0, Planned. Reliability requirements and the qualification standard scoped for the platform.
  • Base Array Design: maturity 0.3, Early draft. Reliability requirements and the qualification standard set for the platform, checked against the integrated base.