One reusable block delivered as a laid out macro for one process and metal stack (hard IP), such as an interface PHY, a clock generator, an IO set, a memory macro or an analog block: from its specification and process choice through circuit design, layout, sign-off and characterised views to a test chip, silicon validation, reliability qualification and a silicon-proven release for SoC teams.
Start here: what it is, how the related terms differ, what this lifecycle covers and its phases in order, then the detail.
Hard IP is a reusable block delivered as finished layout for one process and one metal stack, often called a hard macro. The SoC team places it in its chip as it is, without laying it out again. Typical hard blocks are interface physical layers, high-speed serial links, clock generators, input and output cells, compiled memories and analogue blocks such as data converters.
A block is delivered hard when its behaviour depends on the exact layout: analogue and high-speed circuits, memories packed far denser than general logic, and protection structures tuned to the process. The price of that control is that the block works only on the process and metal stack it was laid out for.
An integrator receives the layout and the views built from it: an abstract with the footprint and pins, timing and power models characterised across corners, circuit models, an integration guide, a datasheet and, once it exists, a silicon report.
Hard IP lifecycle: 9 stages, 14 gates of its own and 2 hand-offs to the Product lifecycle, from Specification & Process Selection to Support, Porting & End of Support.
9 stages, 14 gates of its own and 2 hand-offs to the Product lifecycle, 3 of the gates technical readiness reviews (TR). Each stop opens its stage; each sign opens its gate. Point at a stop or tab to it to read what the stage is for. What the codes mean
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A dashed sign with a TR tag is a technical readiness review gate.
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
In collaboration with The Digital Electronics Blog (opens in a new tab)
Defining what the macro must do and the process it is built on: the target process, metal stack and supply voltages, the interfaces and pin list, the operating corners it must meet, the area and power budget, and the views the integrator will receive.
Hard IP plan approved gate, owned by the Product lifecycle (Plan approval and development commit)TR1: Technology feasibility gateTR1, technical readiness reviewHard IP specification freeze gate
An outlined sign with an arrow is a hand-off: the gate is owned by the Product lifecycle, where this lifecycle hands its work on.
Designing the macro: synthesisable design code for a digital macro, or schematics and circuit simulation for an analog or mixed-signal one, whose circuit work follows the analog and mixed-signal lifecycle.
Verifying the design before layout, by simulation across corners and, for analog circuits, across process variation, and giving SoC teams an early abstract, pin list and preliminary timing model so they can floorplan around the macro.
Turning the design into layout for the target process: placement and routing for a digital macro, custom layout for an analog one, the pins, the power grid and the guard rings, until the layout is complete and the design is frozen.
Running the foundry's sign-off checks on the final layout (design rules, layout against schematic, electrical rules, antenna, electromigration and voltage drop, protection against electrostatic discharge), extracting the parasitics, verifying after layout, and characterising the timing and power views across corners, so the macro can be released to SoC teams before silicon.
Hard macro sign-off gateTR2, technical readiness reviewPre-silicon release gate
Placing the macro on a test chip with the test structures, interface logic and pads needed to measure it, checking the test chip, and releasing its database to the foundry, usually on a shared wafer run.
Bringing up the packaged test chips, measuring the macro across voltage, temperature and process corners, correlating the silicon with the models and views, and running the reliability stresses the macro needs, such as electrostatic discharge, latch-up and high temperature operating life.
Test chip silicon received gateSilicon validated on test chip gateReliability qualified gateTR3, technical readiness review
Checking the complete deliverable set against the quality checklist, with the silicon and reliability evidence, and releasing a versioned, silicon-proven package with its datasheet, integration guide and silicon report.
Supporting the SoC teams that integrate the macro, publishing errata and maintenance releases, following process changes from the foundry, porting the macro to new processes or metal stacks as new versions, and ending support with notice.
Maintenance release gateEnd of support gate, owned by the Product lifecycle (End of support)
| A block delivered as finished layout for one process and metal stack.For example: A memory interface physical layer or a clock generator. |
| Fixed size and performance, proven once; another process means new layout and new silicon proof. |
| Memory compiler | A generator that builds memory macros of a chosen size and shape for one process. | Each generated memory is a hard block, but it is the compiler and its rules that are characterised and proven. |
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| Test chip | A chip made only to measure blocks in silicon. | Not a product; its measurements are the evidence behind a silicon-proven release. |
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| Shuttle | A shared wafer run carrying designs from several teams. | How most test chips are made, so the cost of masks is shared. |
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| Pre-silicon release | Signed-off layout and characterised views released before the test chip results. | Lets an SoC team design in the block early, accepting that it is not yet proven. |
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| Silicon proven | Measured on manufactured silicon on a named process, with a report. | The status most integrators want before they commit a product to the block. |
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The Hard IP lifecycle is the path of one macro on one process: specification and process choice, circuit design and verification, layout, sign-off with the foundry kit and characterisation, then a test chip, silicon validation, reliability qualification and a silicon-proven release, followed by support, maintenance releases and ports.
It differs from the Soft IP lifecycle in where it ends. Soft IP ends in a verified release of design code that each integrator implements. Hard IP ends in layout measured on silicon, so it carries its own tape-out, lab and reliability work, on a test chip that exists only to prove the block.
It runs alongside the SoC lifecycles that use the macro. SoC teams floorplan with its early views, design it in at the pre-silicon release and prefer to commit a product once it is silicon proven.
Gates matter because a hard macro cannot be fixed by the integrator. A wrong pin, a missed corner or a weak protection structure reaches every chip that places it, and the fix is new layout, new sign-off and often a new test chip.
A dotted underline opens the full definition in the glossary.
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Credible sources, named for further reading. Standards are available from the body that publishes them.