Chip lifecycle / Hard IP lifecycle / Physical Sign-off & Characterisation

Physical Sign-off & Characterisation

Running the foundry's sign-off checks on the final layout (design rules, layout against schematic, electrical rules, antenna, electromigration and voltage drop, protection against electrostatic discharge), extracting the parasitics, verifying after layout, and characterising the timing and power views across corners, so the macro can be released to SoC teams before silicon.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^D04 Physical Implementation

^A05 Physical Sign-off & CharacterisationYou are here

^A06 Test Chip Tape-out

IP product milestones

IP engineering milestones

EVEarly views release DLFDesign and layout freeze HMSTR2Hard macro sign-off PSRPre-silicon release

Hard IP architecture^AA

0.8

Circuit and RTL design^AO

0.8

Design verification^A

0.8

1.0

Physical implementation^D

0.8^D

Physical verification and sign-off^A

0.8^A

Characterisation and views^DD

0.8^D

Design for test and test^A

0.5^A

Test chip^A

0.8

1.0

Silicon validation^DA

0.3

Reliability and qualification^A

0.3^A

Foundry and process^A

0.8

1.0

IP quality and release^D

0.5

0.8

Hard IP product management^O

0.5

0.8

Key0.0Specified0.3Pre-alpha0.5Alpha0.8Beta1.0ReleasedLockedFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozen

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Stages

Physical Implementation^D
Physical Sign-off & Characterisation (this stage)^A
Test Chip Tape-out^A

IP product milestones

IP engineering milestones

Early views release (EV)

Physical Sign-off & Characterisation

Where this stage sits

Stages

IP product milestones

IP engineering milestones

Physical Sign-off & Characterisation

Where this stage sits

Stages

IP product milestones

IP engineering milestones

Disciplines

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