Chip lifecycle / Hard IP lifecycle / Test Chip Tape-out

Test Chip Tape-out

Placing the macro on a test chip with the test structures, interface logic and pads needed to measure it, checking the test chip, and releasing its database to the foundry, usually on a shared wafer run.

Where this stage sits

This stage with its neighbours. Each row is a discipline active here, shaded by how mature its work is by the end of each stage.

Stage

^A05 Physical Sign-off & Characterisation

^A06 Test Chip Tape-outYou are here

^D07 Silicon Validation & Reliability

IP product milestones

IP engineering milestones

DLFDesign and layout freeze HMSTR2Hard macro sign-off PSRPre-silicon release TCTTest chip tape-out FSTest chip silicon received SVSilicon validated on test chip RQTR3Reliability qualified

Hard IP architecture^AA

1.0^A

Locked

Circuit and RTL design^AO

1.0

Locked

Design verification^A

1.0

Locked

Physical implementation^D

1.0^O

Locked

Physical verification and sign-off^A

1.0^A

Locked^A

Characterisation and views^DD

1.0^D

Design for test and test^A

0.8^A

1.0

Test chip^A

1.0

Locked^A

Silicon validation^DA

0.5

0.8

1.0^D

Reliability and qualification^A

0.5^A

0.8^A

1.0^A

Foundry and process^A

1.0^A

Locked

IP quality and release^D

0.8^D

Hard IP product management^O

0.8

Key0.0Specified0.3Pre-alpha0.5Alpha0.8Beta1.0ReleasedLockedFaded block: still at the step shown before it, Held below Complete or Maintained under change control once complete or frozenFreeze or sign-off pointMilestone for one item; the rest of the work carries onMilestone gateTRTechnical readiness review (TR): a gate that checks the technology is ready before the next commitment.You are here: Test Chip Tape-outAI impactDisruption (red)Augmentation (blue)Opportunity (green)How AI is changing the workWhat the steps mean What the codes mean

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Stages

IP product milestones

IP engineering milestones

Design and layout freeze (DLF)
Hard macro sign-off (HMS) (technical readiness review TR2)
Pre-silicon release (PSR)
Test chip tape-out (TCT)
Test chip silicon received (FS)
Silicon validated on test chip (SV)
Reliability qualified (RQ) (technical readiness review TR3)

Disciplines

Hard IP architecture^AA
- Physical Sign-off & Characterisation: maturity 1.0, Released. Specification confirmed against the signed-off macro and its characterised views.^A
- Test Chip Tape-out: maturity Locked. Specification locked with the version taped out on the test chip.
Circuit and RTL design^AO
- Physical Sign-off & Characterisation: maturity 1.0, Released. Design final after the fixes from sign-off, matching the signed-off layout.
- Test Chip Tape-out: maturity Locked. Design locked for the test chip; silicon findings and ports go into a new version.; Design locked for the test chip
- Silicon Validation & Reliability: maturity Locked. Design locked for the test chip; silicon findings and ports go into a new version.^A
Design verification^A
- Physical Sign-off & Characterisation: maturity 1.0, Released. Verification on the extracted layout meets the specification at every corner.; Verification after layout complete
- Test Chip Tape-out: maturity Locked. Verification results locked with the test chip version; models compared with silicon.
- Silicon Validation & Reliability: maturity Locked. Verification results locked with the test chip version; models compared with silicon.^A
Physical implementation^D
- Physical Sign-off & Characterisation: maturity 1.0, Released. Layout clean after the sign-off fixes and released as GDS.^O
- Test Chip Tape-out: maturity Locked. Layout locked in the test chip database.; Layout released for the test chip
Physical verification and sign-off^A
- Physical Sign-off & Characterisation: maturity 1.0, Released. Every sign-off check clean or waived with the foundry, and parasitics extracted.^A; Sign-off checks clean
- Test Chip Tape-out: maturity Locked. Test chip checks clean and the sign-off results locked with the database.^A
Characterisation and views^DD
- Physical Sign-off & Characterisation: maturity 1.0, Released. Timing and power views characterised across corners and released before silicon; correlated with silicon after it.^D; Views characterised across corners
- Test Chip Tape-out: maturity 1.0, Released. Timing and power views characterised across corners and released before silicon; correlated with silicon after it.
- Silicon Validation & Reliability: maturity 1.0, Released. Timing and power views characterised across corners and released before silicon; correlated with silicon after it.
Design for test and test^A
- Physical Sign-off & Characterisation: maturity 0.8, Beta. Test patterns generated and simulated on the extracted layout.^A; Test patterns final (milestone for one item)
- Test Chip Tape-out: maturity 1.0, Released. Test chip program working on silicon and production test patterns final.
- Silicon Validation & Reliability: maturity 1.0, Released. Test chip program working on silicon and production test patterns final.
Test chip^A
- Physical Sign-off & Characterisation: maturity 1.0, Released. Test chip assembled around the released layout and checked.
- Test Chip Tape-out: maturity Locked. Test chip database released and locked; packaged parts and boards follow.^A; Test chip database released
- Silicon Validation & Reliability: maturity Locked. Test chip database released and locked; packaged parts and boards follow.^D
Silicon validation^DA
- Physical Sign-off & Characterisation: maturity 0.5, Alpha. Lab set-up and boards being built.
- Test Chip Tape-out: maturity 0.8, Beta. Validation plan and lab ready for first silicon.
- Silicon Validation & Reliability: maturity 1.0, Released. Macro measured across corners on the test chip, with differences listed as errata.^D; Silicon measured across corners
Reliability and qualification^A
- Physical Sign-off & Characterisation: maturity 0.5, Alpha. Reliability qualification plan drafted from the sign-off results.^A
- Test Chip Tape-out: maturity 0.8, Beta. Reliability qualification plan final for the test chip.^A
- Silicon Validation & Reliability: maturity 1.0, Released. Reliability stresses passed on test chips, with failures analysed.
Foundry and process^A
- Physical Sign-off & Characterisation: maturity 1.0, Released. Sign-off kit and rule deck version agreed with the foundry.^A
- Test Chip Tape-out: maturity Locked. Masks made for the test chip and the process version fixed; later process changes are followed.; Test chip masks complete
- Silicon Validation & Reliability: maturity Locked. Masks made for the test chip and the process version fixed; later process changes are followed.
IP quality and release^D
- Physical Sign-off & Characterisation: maturity 0.8, Beta. Deliverables audit before silicon passed; silicon and reliability evidence being collected.^D
- Test Chip Tape-out: maturity 0.8, Beta. Deliverables audit before silicon passed; silicon and reliability evidence being collected.
- Silicon Validation & Reliability: maturity 0.8, Beta. Deliverables audit before silicon passed; silicon and reliability evidence being collected.
Hard IP product management^O
- Physical Sign-off & Characterisation: maturity 0.8, Beta. Pre-silicon release offered to integrators who accept the silicon risk.
- Test Chip Tape-out: maturity 0.8, Beta. Pre-silicon release offered to integrators who accept the silicon risk.
- Silicon Validation & Reliability: maturity 0.8, Beta. Pre-silicon release offered to integrators who accept the silicon risk.

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