Standard · EDA Tools & Flows
LEF (Library Exchange Format)
An ASCII format describing the physical abstract of library cells and macros: outline, pin shapes and layers, obstructions and antenna data. Place and route tools read LEF instead of full GDSII geometry to keep the design database tractable.
- Also known as
- Abstract LEF, Macro LEF
- Type
- Standard
- Domain
- EDA Tools & Flows, Design data formats
Notes
Originated at Cadence, later placed under Si2 stewardship, and paired with DEF as the classic open P&R interchange.
Overview
LEF (Library Exchange Format) is a plain-text format that describes the routing layers of a process and the physical abstract of each library cell or macro, in just enough detail for placement and routing. Instead of full transistor-level layout, a LEF cell gives its outline, the shapes and layers of its pins, and the areas a router must avoid. LEF is used together with DEF, which describes one particular design built from those cells.
How it works
A LEF description has two main parts. The technology part defines each layer in process order from the bottom up, with its type, such as routing or cut, and for routing layers the preferred direction, pitch, width, spacing and resistance and capacitance per unit. It also defines vias and rules for generating via arrays, and a manufacturing grid. The library part defines sites, the unit grid on which rows of cells are placed, and macros, one per cell or block. The technology part is often kept in its own file, commonly called a technology LEF.
Each macro gives a class, such as core, pad or block, a size, the site it uses and a symmetry that tells the placer which flips and rotations are allowed. Pin statements give the direction and use of each pin, such as signal, power, ground or clock, and one or more ports made of rectangles or polygons on named layers. Obstruction statements mark metal inside the cell that routes must not touch, and layers can carry antenna data.
LEF and DEF were created at Tangent Systems for its place and route tools, passed to Cadence when it bought those tools in 1989, and were later opened up. Si2 now distributes them under the Apache 2.0 licence, with releases in the 5.8 and 6.0 series. Because LEF leaves out internal cell detail, it keeps design databases small, but it must stay consistent with the full layout and the timing views of the same cells.
Examples
- A technology LEF defining each metal layer's preferred direction, pitch and spacing, read at the start of a place and route session.
- A cell LEF for a two-input NAND gate giving its size in placement sites, its input and output pin shapes and its power and ground pins.
- The LEF views shipped with the open SKY130 libraries, alongside GDS, Liberty, SPICE and Verilog views of the same cells.
Why it matters
Standard cell library and PDK teams produce LEF, floorplanning and physical design engineers consume it, and EDA developers write the readers. A pin shape that does not match the real layout, or a missing obstruction, can cause shorts, opens or rule violations that only appear at signoff, so library LEF is checked carefully against the full layout.
In the chip lifecycle, LEF arrives with the PDK and IP deliverables before physical design, is used throughout floorplanning, placement and routing, and gives way to full layout data when the design is streamed out at tapeout.
It matters most to: EDA R&D Engineer, Place and Route, Floorplanning Engineer, PDK Development Engineer, Physical Design Engineer, Standard Cell Library Engineer
Common confusions
- Not the same as DEF
- DEF, the Design Exchange Format, describes one design: its constraints, layout and netlist, including placed instances and routing. LEF describes the library and technology that the design uses. LEF vs DEF
- Not the same as GDSII
- GDSII holds the complete layout geometry used to make masks. A LEF cell is an abstract with only its outline, pins and blockages, which is all a router needs.
- Not the same as Liberty
- A Liberty file models a cell's timing, power, noise and test behaviour. LEF describes its physical shape. Place and route tools need both. LEF vs Liberty
Sources
- LEF/DEF Downloads (opens in a new tab), Si2, 2026-10-22
- Standard Cell Library/Library Exchange Format (LEF), CMPE 641 Advanced VLSI Design lecture slides (opens in a new tab), University of Maryland, Baltimore County, 2026-10-22
- open_pdks: PDK installer for open-source EDA tools (README) (opens in a new tab), FOSSi Foundation, GitHub, 2026-10-22
- Technology Access Program (TAP-in) (opens in a new tab), Synopsys, 2026-10-22
- LEF/DEF (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
Related terms
Part of the EDA Tools & Flows glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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