Hard IP Design Engineer

Project

Work done for a product or program.

• Design transistor-level circuits for PHY building blocks such as CTLE, DFE, CDR, PLL, charge pump, bias and LDO regulators against the protocol electrical specification.
• Run schematic-level simulation across PVT corners, Monte Carlo mismatch and aging in Cadence Spectre and Siemens Eldo, including jitter and BER-bathtub analysis for SerDes.
• Build and maintain the mixed-signal testbench connecting the analog macro to the digital controller using Verilog-AMS and real-number models.
• Own floorplan, device placement, matching, shielding and custom routing of the hard macro with the layout team in Cadence Virtuoso.
• Close parasitic-aware post-layout simulation using StarRC or Quantus extraction and iterate layout to meet insertion loss, return loss and jitter budgets.
• Perform electromigration, IR-drop, ESD and latch-up analysis and sign off reliability rules with the foundry design rule manual.
• Port and re-characterise the macro to new process nodes and foundries, re-centring bias and trim ranges against updated SPICE models.
• Support silicon bring-up on the test chip, correlating bench eye diagrams and PLL phase noise against simulation and identifying re-spin fixes.
• Author the electrical section of the IP datasheet including operating conditions, trim/calibration procedure and integration constraints.

Function

Work that keeps the discipline running: methods, tools, suppliers and people.

• Maintain design guidelines, coding standards and reusable blocks.General
• Improve design flows and checks with the CAD and methodology teams.General
• Mentor newer engineers and share lessons learned across projects.General

Project

1. Produce and hand over the role's key deliverables
   • Transistor-level schematics and PVT/Monte Carlo simulation sign-off database
   • Hardened macro GDSII with LEF abstract and CDL netlist
   • Verilog-AMS and real-number behavioural models for SoC-level simulation
   • Electrical characterisation report and datasheet electrical tables
   • Reliability sign-off package (EM/IR, ESD, latch-up, aging)
2. Design the blockGeneral
   • Write or capture the design to the specification
   • Run lint, simulation or circuit checks
   • Close design reviews and their actions
3. Support integration and sign-offGeneral
   • Fix bugs found by verification
   • Support timing and physical closure
   • Deliver handoff files and documentation

Function

1. Keep design methods currentGeneral
   • Maintain coding and design standards
   • Build and maintain reusable blocks
2. Develop peopleGeneral
   • Mentor newer engineers
   • Run design reviews and knowledge sharing sessions