Standard cell library

Notes

Libraries are usually sold or licensed by the foundry or an IP vendor such as Arm rather than built by the chip team.

Overview

A standard cell library is the complete, characterised set of logic gates, flip-flops, buffers and special-purpose cells that a digital design flow builds chips from, delivered for one specific process. Each cell comes in several views: timing and power models for synthesis and timing analysis, a physical abstract for place and route, full layout for mask data, and netlists and models for simulation. Foundries and IP vendors often offer several libraries for one process, tuned for density, speed or low leakage.

How it works

Every cell in a library has the same height, so cells can be placed side by side in rows with power and ground running along each row. A library usually offers each logic function in several versions that trade area for speed, plus special cells such as clock gating cells, retention flip-flops, tie cells, fillers and decoupling capacitors. The views shipped for each cell typically include GDS layout, a LEF abstract, Liberty timing and power models, SPICE or CDL netlists and Verilog models; the open SKY130 libraries, for example, come with all of these.

The Liberty models come from characterisation: each cell is simulated at transistor level across input transitions, output loads and operating conditions, and the resulting tables of delay, transition, power and capacitance are stored for the tools. Liberty itself, which Synopsys publishes through its TAP-in programme, models timing, noise, power and test behaviour at gate level.

Libraries within one process are tuned in different ways. SkyWater's 130 nm process has seven foundry libraries, including a high-density library on a 0.46 by 2.72 micrometre site, a low-leakage version of it with five to ten times lower leakage, high, medium and low speed libraries on a taller site, a low-power library of nearly 750 cells and a 5 V library. Picking a library and its options is one of the first physical decisions in a project, because it fixes much of the balance between area, speed and leakage.

Examples

• The sky130_fd_sc_hd high-density library for SkyWater's 130 nm process, quoted at a routed density of 160 thousand gates per square millimetre or better.
• SkyWater's medium-speed sky130_fd_sc_ms library, which supports low-leakage sleep modes through state-retention flip-flops.
• A low-leakage library variant chosen for always-on logic in a battery-powered device.
• A library offered in several threshold-voltage flavours so that critical paths use fast cells while other logic saves leakage.

Related terms

• Liberty
• LEF
• Track height
• Drive strength
• Multi-Vt

Where it appears on the Hub

Used on 17 pages of the Hub. In each group, the pages that mention it most come first.