Standard cell

Overview

A standard cell is a small, pre-designed and pre-characterised layout of transistors that performs one logic function, such as an inverter, NAND gate, multiplexer or flip-flop, built to a fixed height so that cells can be placed side by side in rows. Synthesis tools build digital logic out of these cells, and place-and-route tools arrange and wire them automatically. Cells are supplied in libraries for each process, by the foundry, an IP vendor or an in-house team.

How it works

All cells in a library share one height, usually described by the number of horizontal routing tracks it spans, and vary in width with complexity. Power and ground rails run along the edges of each row, so neighbouring cells join up automatically. Inside, transistors and local wiring are drawn, often by hand, as densely as the design rules allow, with pins placed where the router can reach them easily.

A library offers each function in several drive strengths and often several threshold-voltage variants, trading speed against leakage. It is delivered as a set of views: the layout for manufacturing, an abstract with pin and blockage shapes for place and route, a transistor netlist for LVS, simulation models, and timing and power models in the Liberty format. Those models come from characterisation, in which each cell is simulated at transistor level across process, voltage and temperature conditions.

Libraries come in families for different goals. SkyWater's open 130 nm process, for example, has seven foundry-provided libraries, including high-density cells nine metal-one tracks tall and high-speed, medium-speed, low-speed and low-power cells eleven tracks tall. Taller cells generally favour speed, and shorter ones favour density, power and cost. Libraries also include special cells such as integrated clock gates, multi-bit flip-flops, cells for power shut-down and multiple voltage domains, tap cells and ECO cells for metal-only fixes.

Examples

• The sky130_fd_sc_hd library, SkyWater's high-density cell set for its 130 nm process, openly available for SKY130 designs.
• A flip-flop offered in several drive strengths and threshold-voltage variants so that synthesis can choose speed or low leakage path by path.
• Multi-bit flip-flops that combine several storage bits in one cell to save area.
• Integrated clock gating cells that switch off the clock to idle logic to save dynamic power.

Why it matters

Standard cells are the building blocks of most digital chips, so their quality sets a floor on performance, power and area. Library design, layout and characterisation engineers create and validate them, while synthesis, place-and-route and timing engineers depend on them, and choosing the library family and threshold-voltage mix is one of the first decisions in a digital implementation.

In the chip lifecycle, libraries are developed alongside a new process and its PDK, chosen during architecture and implementation planning, used through synthesis, place and route and signoff, and re-characterised when process models change.

It matters most to: Foundation IP Engineer, Library Characterization Engineer, RTL Synthesis Engineer, Standard Cell & Bitcell Layout Engineer, Standard Cell Library Design Engineer

Common confusions

Not the same as a memory bitcell

A bitcell stores one bit inside an SRAM array and is laid out to much tighter, array-specific rules. Standard cells are general logic placed individually by tools.

Not the same as a standard cell library

The library is the whole collection with its views and models. A standard cell is one entry in it.

Not the same as a gate array

In a gate array the transistors are prefabricated and only the wiring is customised. A standard cell design customises every layer, with cells placed wherever the design needs them.

Sources

1. SkyWater Foundry Provided Standard Cell Libraries (SKY130 PDK documentation) (opens in a new tab), SkyWater Technology, 2026-10-22
2. Logic Library IP (opens in a new tab), Synopsys, 2026-10-22
3. OpenROAD (project documentation) (opens in a new tab), The OpenROAD Project, 2026-10-22
4. Standard cell (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• Standard cell library
• Standard cell row
• Liberty
• Logic synthesis

Where it appears on the Hub

Used on 23 pages of the Hub. In each group, the pages that mention it most come first.