Priority-Aware Deficit Round Robin for AXI4 Bandwidth Fairness in ASAP-7nm Process

Modern systems-on-chip place real-time clients, processor cores and bulk data engines on the same AXI4 interconnect, where they contend for shared slaves. AXI4 fixes the ordering rules and carries a 4-bit quality of service (QoS) field, but leaves the service policy to the implementer, and that policy determines how long each master waits and how much bandwidth it receives once a slave saturates. We propose a QoS-aware deficit round robin (DRR) architecture that charges each grant in beats, and…

Source: arXiv cs.AR (Hardware Architecture), published 2026-11-11. The summary is the Hub's own; the full story is at the source. Report a rights or accuracy concern