Glossary

F

Failure analysisProcess

The disciplined investigation of a failed device, moving from non-destructive checks and electrical characterisation through fault localisation to physical inspection, in order to identify the failure mechanism and feed root cause analysis.

Also known as: FA

Sequence discipline is everything, because the destructive steps that reveal the defect also destroy the evidence for every earlier technique.

Reliability & Quality· Failure analysis

In the lifecycles:Post-EOL Support (Product lifecycle),Last-time ship (SoC lifecycle),Package Qualification & Production Release (Chiplet lifecycle)

Related: EFA, PFA, RCA, Decapsulation

Fault injection simulationProcess

Verification that deliberately forces stuck-at or transient faults into an RTL or gate-level model and checks whether the safety mechanisms detect them. It supplies measured diagnostic coverage evidence rather than expert estimates.

Also known as: Fault campaign, Safety verification

Formal methods are increasingly used first to prove faults structurally unobservable, shrinking the simulation campaign.

Safety & Security· Safety analysis

In the lifecycles:Security Verification (Security lifecycle),Security verification sign-off (Security lifecycle)

Related: Diagnostic coverage, FMEDA, Formal safety analysis, Safe fault

Fault injection testingProcess

Deliberately introducing errors, such as corrupted memory, stuck sensor values, bus failures or flipped bits, to verify that detection and safe-state mechanisms work. ISO 26262 expects it as evidence that safety mechanisms achieve their claimed coverage.

Also known as: Fault injection, FI testing

It can be done in simulation, on a debugger by corrupting registers, or physically by forcing signals on a harness.

Embedded Software & Tools· Software quality and safety

In the lifecycles:Safety Verification & Fault Injection (Automotive lifecycle),Verification and safety verification sign-off (Automotive lifecycle),Verification & Fault Injection (Space lifecycle)

Related: ASIL decomposition, HIL, Freedom from interference, On-target test

Fault simulationProcess

Simulating a circuit with a fault deliberately injected to determine whether a given pattern set detects it. It is used to grade functional patterns, to credit coverage without generating new vectors, and to build dictionaries for diagnosis.

Also known as: Fault grading

Concurrent and parallel-pattern algorithms make it fast enough that ATPG engines run it continuously to drop already-detected faults.

Test & DFT· ATPG and fault models

Related: ATPG, Fault coverage, Scan diagnosis, Functional test

Feature freezeProcess

The point after which no new functionality may be added to a product, though bug fixes continue. It marks the transition from building the thing to making the thing correct.

Feature freeze dates are typically set backwards from tape-out by the verification team's estimate of regression closure time.

General Industry· Programme jargon

Related: Design freeze, Code freeze, Spec freeze, Scope creep

Fibre attachProcess

The assembly step that aligns and permanently fixes optical fibre or a fibre array unit to a photonic die or module, usually with index-matching epoxy or laser welding. Sub-micron placement accuracy makes it a throughput and yield bottleneck.

Also known as: Fiber attach, Fibre coupling

Photonic packaging often costs more than the photonic die itself, largely because of alignment-limited fibre attach.

Photonics, MEMS & Sensors· Packaging and assembly

In the lifecycles:Packaging & Fibre Attach (Photonics lifecycle),Reliability Qualification (Photonics lifecycle),Assembly process qualified (Photonics lifecycle)

Related: Edge coupler, Grating coupler, Optical engine, Optical transceiver

Final testProcess

Electrical test of the packaged device on automated test equipment, after assembly, typically across temperature and using a handler and load board rather than a wafer prober. It produces the bins that determine part number and speed grade.

Also known as: FT, Package test, Class test

Test time per part directly drives cost, so test content is continually traded against escape rate and coverage.

Packaging & Assembly· Assembly and test operations

In the lifecycles:Packaging & Test (SoC lifecycle),First packaged parts tested (SoC lifecycle),Final & System-Level Test (Chiplet lifecycle)

Related: SLT, Burn-in, OSAT, KGD, Wafer sort, Handler

Formal verificationProcess

Mathematical proof that a design satisfies properties for all legal inputs, rather than for the specific stimulus a simulation happened to apply. It gives exhaustive results on bounded problems and is complementary to, not a replacement for, simulation.

Also known as: FV, Formal property verification, FPV

Practical on control logic, arbiters, FIFOs and protocol bridges; datapath and large sequential depth remain difficult.

Verification & Validation· Formal verification

In the lifecycles:Implementation and Integration (Avionics lifecycle),Build baselined (Avionics lifecycle)

Related: Model checking, Equivalence checking, Formal app, Assumption

FracturingProcess

Decomposing OPC-corrected polygons into the primitive shapes a mask writer can expose, typically trapezoids for variable shaped beam tools, and ordering them into the writer's job format.

Also known as: Mask fracturing, Shot decomposition

Shot count directly sets mask write time and cost, so fracture efficiency is an economic as well as technical concern.

Physical Design & Signoff· Mask data prep

Related: MDP, OPC

Front-endProcess

Wafer fabrication from bare wafer to completed wafer, covering transistor formation, interconnect and all cleanroom processing. Front-end capacity is measured in wafer starts and is where the overwhelming majority of a fab's capital is sunk.

Also known as: Front-end manufacturing, Wafer fab

Confusingly, front-end in design conversations means RTL and verification, while front-end in manufacturing means the fab.

General Industry· Value chain and business models

In the lifecycles:Architecture & Link Budget (RF lifecycle),Architecture and link budget baseline (RF lifecycle)

Related: Back-end, Fab, WSPM, Upstream

Fusion bondingProcess

Direct wafer bonding where two clean, flat, activated surfaces join by van der Waals forces and are then annealed into covalent bonds, without any intermediate adhesive layer.

Also known as: Direct bonding, Silicon direct bonding

Demands sub-nanometre surface roughness and near-perfect cleanliness, so it is the least forgiving of the bonding options.

Photonics, MEMS & Sensors· MEMS

Related: Anodic bonding, Eutectic bonding, SOI-MEMS, Cap wafer