UPF (Unified Power Format)

Notes

IEEE 1801 absorbed the rival CPF effort, making UPF the single surviving power intent standard.

Overview

UPF (Unified Power Format) is the IEEE 1801 language for writing down a chip's power intent: which parts of the design sit in which power domains, how they are supplied and switched, and what isolation, retention and level shifting are needed where domains meet. It is written as Tcl commands in files kept alongside the RTL rather than inside it. Simulation, synthesis, place-and-route and signoff tools all read the UPF, which keeps the low-power structures consistent from verification to silicon.

How it works

UPF extends Tcl with commands that annotate a design hierarchy already loaded into a tool. A typical file declares the power domains and the instances each contains, the supply ports, nets and sets that feed them, and the power switches that can turn a domain off. It then sets strategies: isolation, which holds the outputs of a powered-down domain at safe values; retention, which keeps chosen register state while power is off; and level shifting, for signals that cross between different voltages. Finally it records the power states the system may legally be in. UPF states what must happen, not how a tool must achieve it.

Tools act on the intent in stages. Power-aware simulation shows what happens when domains switch off and on, including whether the control sequence is correct. Synthesis reads the RTL, SDC and UPF, inserts isolation, level shifter and retention cells, and writes an updated UPF; physical implementation adds power switches and routes the supplies, writing a further refined UPF; and static checkers confirm that each stage is consistent with the original intent. The standard supports incremental refinement, so a block's intent written by an IP provider can be extended by the SoC team.

Accellera approved UPF 1.0 in February 2007 and handed it to the IEEE, which published IEEE 1801-2009 and later revisions. The current edition is IEEE 1801-2024, approved in September 2024.

Examples

• A mobile SoC that switches off its graphics domain when idle, with UPF describing the power switch, isolation on the domain's outputs and retention for selected registers.
• An IP vendor shipping a block-level UPF file with a processor core, which the SoC team refines and merges into the chip-level power intent.
• A static check confirming that every signal crossing between two supply voltages passes through a level shifter.

Why it matters

Low-power design, implementation and verification engineers write and check UPF, and power architects use it to make their decisions concrete. Mistakes are costly: a missing isolation cell or a wrong power-up sequence may not show in ordinary RTL simulation, yet can corrupt signals or stop a chip waking from sleep.

Related terms

• CPF
• Power domain
• Clock gating
• Signoff
• Level shifter
• Power-aware simulation

Where it appears on the Hub

Used on 17 pages of the Hub. In each group, the pages that mention it most come first.