Term · Design & Architecture
Power intent
The description of how a design's power is managed, separate from its logic: its power domains, supplies, switches, isolation, retention and level shifters. It is written in a format such as UPF so that every tool in the flow implements and checks the same intent.
- Type
- Term
- Domain
- Design & Architecture, Low power design
Overview
Power intent is the description of how a chip's power is to be managed, kept separate from its logic: which blocks share a supply, which can be switched off or run at a different voltage, and what protection is needed at the boundaries between them. Architects decide it, and engineers capture it in a machine-readable form, most commonly the IEEE 1801 Unified Power Format (UPF), so that every tool in the flow implements and checks the same plan. Keeping it out of the RTL helps when the same block is reused in chips with different power arrangements.
How it works
Power intent combines a few main techniques. Multi-voltage design runs high-performance blocks at a higher supply and less demanding ones at a lower supply, creating voltage islands. Power gating connects a domain's supply through switches so that a block can be turned off completely when idle, removing its leakage. Clock gating stops the clock to idle logic to cut switching power, and dynamic voltage and frequency scaling adjusts supply and speed to the workload.
Each technique adds requirements that the power intent must spell out. Signals crossing between voltage islands may need level shifters. The outputs of a switched-off domain must be held at known values by isolation cells while it is off. Registers whose contents must survive shutdown need retention flip-flops with save and restore signals. A power management unit must switch domains, enable isolation and handle retention in the right order, and the allowed combinations of on, off and voltage levels form the system's power states.
Once captured in UPF, the intent is checked statically alongside the RTL and timing constraints, exercised in power-aware simulation, used by synthesis to insert the special cells and by physical implementation to add power switches and route the supplies, and finally checked for consistency at signoff.
Examples
- A mobile SoC that runs its application processors at a higher voltage than an always-on sensor hub, with level shifters on every signal between them.
- Retention flip-flops in a modem block that keep configuration state while the rest of the block is powered down.
- A power management unit that enables isolation before switching a domain off and restores retained state after power returns.
- An IP block delivered with its own power intent, which the SoC team refines and merges into the chip-level description.
Why it matters
Power architects set the power intent, low-power design, implementation and verification engineers capture and check it, and power management software engineers later drive the sequences it defines. It decides battery life and thermal headroom, and errors in it can leave a chip that wastes power, corrupts data on wake-up or fails to power up at all.
In the chip lifecycle, power intent is defined at architecture, captured with the RTL, verified before synthesis, implemented during synthesis and physical design, checked at signoff before tapeout, and exercised in silicon by firmware and power management software during bring-up.
It matters most to: Low-Power Design Engineer, Low-Power Implementation Engineer, Low-Power Verification Engineer, Power Architect, Power Management Software Engineer
Common confusions
- Not the same as UPF
- UPF is the language; power intent is what it describes. The same intent could be written in another format, such as Si2's Common Power Format (CPF), whose development Si2 archived in 2014. Power intent vs UPF
- Not the same as power integrity
- Power integrity is about delivering a clean, stable supply voltage with limited drop and noise. Power intent is about how supplies are organised and switched.
- Not the same as power analysis
- Power analysis estimates how much power a design consumes. Power intent states how that power is structured and controlled.
Related standards
- IEEE 1801 (design and verification of low-power, energy-aware electronic systems, known as UPF)
Sources
- What is Low Power Design? (opens in a new tab), Synopsys, 2026-10-22
- IEEE 1801-2024: IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic Systems (opens in a new tab), IEEE Standards Association, 2026-10-22
- Si2 OpenStandards (opens in a new tab), Si2, 2026-10-22
- Unified Power Format (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22
Related terms
Part of the Design & Architecture glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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