Standard · EDA Tools & Flows
Verilog netlist
A gate-level structural description written in Verilog syntax, containing only library cell instantiations and wire declarations. It is the standard handoff from synthesis to place and route, formal equivalence checking and gate-level simulation.
- Also known as
- Structural Verilog, .v netlist
- Type
- Standard
- Domain
- EDA Tools & Flows, Design data formats
Notes
Despite decades of alternatives, plain structural Verilog remains the most portable way to move a digital design between vendors.
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